Cypress CY7C64013C, CY7C64113C t OED t, t

CY7C64013C
CY7C64113C
Document #: 38-08001 Rev. *B Page 47 of 51
Figure 24-1. Clock Timing
Figure 24-2. USB Data Signal Timing
Figure 24-3. HAPI Read by External Interface from USB Microcontroller
CLOCK
tCYC
tCL
tCH
90%
10%
90%
10%
D−
D+
trtr
OE (P2.5, input)
DATA (output)
STB (P2.4, input)
DReadyPin (P2.3, output)
Internal Write
Internal Addr Port0
D[23:0]
tOED tOEZ
tRD
tOEDR
CS (P2.6, input)
Int
(Shown for DRDY Polarity=0)
Interrupt Generated
(Ready)
[+] Feedback