Cypress CY8C24423, CY8C24123, CY8C24223 manual PSoC Functional Overview, PSoC Core, Digital System

CY8C24123 CY8C24223, CY8C24423

PSoC® Functional Overview

The PSoC® family consists of many Mixed Signal Array with On-Chip Controller devices. These devices are designed to replace multiple traditional MCU-based system components with one, low cost single-chip programmable device. PSoC devices include configurable blocks of analog and digital logic, and programmable interconnects. This architecture allows the user to create customized peripheral configurations that match the requirements of each individual application. Additionally, a fast CPU, Flash program memory, SRAM data memory, and config- urable IO are included in a range of convenient pinouts and packages.

The PSoC architecture, as shown in the Logic Block Diagram on page 1, is comprised of four main areas: PSoC Core, Digital System, Analog System, and System Resources. Configurable global busing allows all the device resources to be combined into a complete custom system. The PSoC CY8C24x23 family can have up to three IO ports that connect to the global digital and analog interconnects, providing access to four digital blocks and 6 analog blocks.

PSoC Core

The PSoC Core is a powerful engine that supports a rich feature set. The core includes a CPU, memory, clocks, and configurable GPIO (General Purpose IO).

The M8C CPU core is a powerful processor with speeds up to 24 MHz, providing a four MIPS 8-bit Harvard architecture microprocessor. The CPU uses an interrupt controller with 11 vectors, to simplify programming of real time embedded events. Program execution is timed and protected using the included Sleep and Watch Dog Timers (WDT).

Memory encompasses 4 KB of Flash for program storage, 256 bytes of SRAM for data storage, and up to 2 KB of EEPROM emulated using the Flash. Program Flash uses four protection levels on blocks of 64 bytes, allowing customized software IP protection.

The PSoC device incorporates flexible internal clock generators, including a 24 MHz IMO (internal main oscillator) accurate to 2.5% over temperature and voltage. The 24 MHz IMO can also be doubled to 48 MHz for use by the digital system. A low power 32 kHz ILO (internal low speed oscillator) is provided for the Sleep timer and WDT. If crystal accuracy is desired, the ECO (32.768 kHz external crystal oscillator) is available for use as a Real Time Clock (RTC) and can optionally generate a crystal-accurate 24 MHz system clock using a PLL. The clocks, together with programmable clock dividers (as a System Resource), provide the flexibility to integrate almost any timing requirement into the PSoC device.

PSoC GPIOs provide connection to the CPU, digital and analog resources of the device. Each pin’s drive mode may be selected from eight options, allowing great flexibility in external inter- facing. Every pin also has the capability to generate a system interrupt on high level, low level, and change from last read.

Digital System

The Digital System is composed of four digital PSoC blocks. Each block is an 8-bit resource that can be used alone or combined with other blocks to form 8, 16, 24, and 32-bit peripherals, which are called user module references.

Figure 1. Digital System Block Diagram

Port 2 Port 1 Port 0

Digital Clocks			To System Bus		To Analog
From Core					System
		DIGITAL SYSTEM
		Digital PSoC Block Array
8	Configuration		Row 0		4	Row Output Configuration	8
8		DBB00	DBB01	DCB02	DCB03		8
RowInput
					4
		GIE[7:0]	Global Digital		GOE[7:0]
		GIO[7:0]	Interconnect		GOO[7:0]

Digital peripheral configurations include:

■PWMs (8 to 32 bit)

■PWMs with Dead band (8 to 32 bit)

■Counters (8 to 32 bit)

■Timers (8 to 32 bit)

■UART 8-bit with selectable parity (up to one)

■SPI master and slave (up to one)

■I2C slave and master (one available as a System Resource)

■Cyclical Redundancy Checker/Generator (8 to 32 bit)

■IrDA (up to one)

■Pseudo Random Sequence Generators (8 to 32 bit)

The digital blocks can be connected to any GPIO through a series of global buses that can route any signal to any pin. The buses also allow for signal multiplexing and for performing logic operations. This configurability frees your designs from the constraints of a fixed peripheral controller.

Digital blocks are provided in rows of four, where the number of blocks varies by PSoC device family. This allows the optimum choice of system resources for your application. Family resources are listed in the table PSoC Device Characteristics on page 4.

Document Number: 38-12011 Rev. *G Page 2 of 43

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