CY8C24123
CY8C24223, CY8C24423
Document Number: 38-12011 Rev. *G Page 34 of 43
AC External Clock Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only or unless otherwise specified.
AC Programming Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only or unless otherwise specified.
Table 32. 5V AC External Clock Specifications
Symbol Description Min Typ Max Units
FOSCEXT Frequency 0 – 24.24 MHz
– High Period 20.6 ––ns
– Low Period 20.6 ––ns
– Power Up IMO to Switch 150 – – μs
Table 33. 3.3V AC External Clock Specifications
Symbol Description Min Typ Max Units
FOSCEXT Frequency with CPU Clock divide by 1a0– 12.12 MHz
FOSCEXT Frequency with CPU Clock divide by 2 or greaterb0– 24.24 MHz
– High Period with CPU Clock divide by 1 41.7 ––ns
– Low Period with CPU Clock divide by 1 41.7 ––ns
– Power Up IMO to Switch 150 – – μs
a. Maximum CPU frequency is 12 MHz at 3.3V. With the CPU clock divider set to 1, the external clock must adhere to the maximum frequency and duty cycle
requirements.
b. If the frequency of the external clock is greater than 12 MHz, the CPU clock divider must be set to 2 or greater. In this case, the CPU clock divider ensures
that the fifty percent duty cycle requirement is met.
Table 34. AC Programming Specifications
Symbol Description Min Typ Max Units
TRSCLK Rise Time of SCLK 1 – 20 ns
TFSCLK Fall Time of SCLK 1 – 20 ns
TSSCLK Data Set up Time to Falling Edge of SCLK 40 – – ns
THSCLK Data Hold Time from Falling Edge of SCLK 40 – – ns
FSCLK Frequency of SCLK 0 – 8 MHz
TERASEB Flash Erase Time (Block) –15 –ms
TWRITE Flash Block Write Time –30 –ms
TDSCLK Data Out Delay from Falling Edge of SCLK – – 45 ns
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