Cypress CY8C24423, CY8C24123 Input Capacitance Port 0 Analog Pins Package and pin, Open Loop Gain

CY8C24123

CY8C24223, CY8C24423

Table 16. 3.3V DC Operational Amplifier Specifications

Symbol	Description	Min	Typ	Max	Units	Notes
VOSOA	Input Offset Voltage (absolute value) Low Power	–	1.65	10	mV
	Input Offset Voltage (absolute value) Mid Power	–	1.32	8	mV
	High Power is 5 Volt Only
TCVOSOA	Average Input Offset Voltage Drift	–	7.0	35.0	μV/oC
IEBOA	Input Leakage Current (Port 0 Analog Pins)	–	20	–	pA	Gross tested to 1 μA.
CINOA	Input Capacitance (Port 0 Analog Pins)	–	4.5	9.5	pF	Package and pin
						dependent. Temp = 25oC.
VCMOA	Common Mode Voltage Range	0.2	–	Vdd - 0.2	V	The common-mode input
						voltage range is
						measured through an
						analog output buffer. The
						specification includes the
						limitations imposed by the
						characteristics of the
						analog output buffer.
GOLOA	Open Loop Gain	60	–	–	dB	Specification is applicable
	Power = Low					at high power. For all
	Power = Medium	60				other bias modes (except
	Power = High	80				high power, high opamp
						bias), minimum is 60 dB.
VOHIGHOA	High Output Voltage Swing (worst case internal load)	Vdd - 0.2	–	–	V
	Power = Low
	Power = Medium	Vdd - 0.2	–	–	V
	Power = High is 5V only	Vdd - 0.2	–	–	V
VOLOWOA	Low Output Voltage Swing (worst case internal load)	–	–	0.2	V
	Power = Low
	Power = Medium	–	–	0.2	V
	Power = High	–	–	0.2	V
ISOA	Supply Current (including associated AGND buffer)	–	150	200	μA
	Power = Low
	Power = Low, Opamp Bias = High	–	300	400	μA
	Power = Medium	–	600	800	μA
	Power = Medium, Opamp Bias = High	–	1200	1600	μA
	Power = High	–	2400	3200	μA
	Power = High, Opamp Bias = High	–	4600	6400	μA
PSRROA	Supply Voltage Rejection Ratio	50	–	–	dB

Document Number: 38-12011 Rev. *G Page 20 of 43

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