CY8C24094, CY8C24794
CY8C24894, CY8C24994
Document Number: 38-12018 Rev. *M Page 14 of 47
Figure 8-6. CY8C24094 OCD (Not for Production)C8 I/O I,M P2[0] Direct switched capacitor block input. H8 I/O M P3[2]
C9 I/O MP4[2] H9 I/O MP5[4]
C10 NC No connection. H10 I/O P7[3]
D1 NC No connection. J1 Power Vss Ground connection.
D2 I/O MP3[7] J2 Power Vss Ground connection.
D3 I/O MP4[5] J3 USB D+
D4 I/O M P2[5] J4 USB D-
D5 I/O I/O,
MP0[3] Analog column mux input and column output. J5 Power Vdd Supply voltage.
D6 I/O I,M P0[4] Analog column mux input. J6 I/O P7[7]
D7 I/O M P2[6] External Voltage Reference (VREF) input. J7 I/O P7[0]
D8 I/O MP4[6] J8 I/O M P5[2]
D9 I/O MP4[0] J9 Power Vss Ground connection.
D10 CCLK OCD CPU clock output. J10 Power Vss Ground connection.
E1 NC No connection. K1 Power Vss Ground connection.
E2 NC No connection. K2 Power Vss Ground connection.
E3 I/O MP4[3] K3 NC No connection.
E4 I/O I,M P2[3] Direct switched capacitor block input. K4 NC No connection.
E5 Power Vss Ground connection. K5 Power Vdd Supply voltage.
E6 Power Vss Ground connection. K6 I/O P7[6]
E7 I/O MP2[4] External Analog Ground (AGND) input. K7 I/O P7[5]
E8 I/O MP4[4] K8 I/O P7[4]
E9 I/O MP3[6] K9 Power Vss Ground connection.
E10 HCLK OCD high-speed clock output. K10 Power Vss Ground connection.
LEGENDA = Analog, I = Input, O = Output, M = Analog Mux Input, NC = No Connection, OCD = On-Chip Debugger.
Table 8-6. 100-Ball Part Pinout (VFBGA) (continued)Vss Vss NC NC NC Vdd NC NC Vss Vss
Vss Vss P2[1] P0[1] P0[7] Vdd P0[2] P2[2] Vss Vss
NC P4[1] P4[7] P2[7] P0[5] P0[6] P0[ 0] P2[0] P4[2] NC
NC P3[7] P4[5] P2[5] P0[3] P0[4] P2[ 6] P4[6] P4[0] CClk
NC NC P4[3] P2[3] Vss Vss P2[4] P4[4] P3[6] HClk
ocde P5[7] P3[5] P5[1] Vss Vs s P5[0] P3[0] XRES P7[1]
ocdo P5[5] P3[3] P1[7] P1[1] P1[ 0] P1[6] P3[4] P5[6] P7[2]
NC P5[3] P3[1] P1[5] P1[3] P1[2] P1[ 4] P3[2] P5[4] P7[3]
Vss Vss D + D - Vdd P7[7] P7[0] P5[2] Vss Vss
Vss Vss NC NC Vdd P7[6] P7[ 5] P7[4] Vss Vss
12345678910
A
B
C
D
E
F
G
H
J
K
BGA (Top View)
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