Cypress CY8C24994, CY8C24094, CY8C24894 manual Pin Part Pinout On-Chip Debug, Pin Part Pinout Tqfp

CY8C24094, CY8C24794

CY8C24894, CY8C24994

8.1 100-Pin Part Pinout (On-Chip Debug)

The 100-pin TQFP part is for the CY8C24094 On-Chip Debug (OCD) PSoC device.

Note This part is only used for in-circuit debugging. It is NOT available for production.

Table 8-7. 100-Pin Part Pinout (TQFP)

Pin	Digital	Analog	Name	Description	Pin	Digital	Analog	Name	Description
No.					No.
1			NC	No connection.	51	I/O	M	P1[6]
2			NC	No connection.	52	I/O	M	P5[0]
3	I/O	I, M	P0[1]	Analog column mux input.	53	I/O	M	P5[2]
4	I/O	M	P2[7]		54	I/O	M	P5[4]
5	I/O	M	P2[5]		55	I/O	M	P5[6]
6	I/O	I, M	P2[3]	Direct switched capacitor block input.	56	I/O	M	P3[0]
7	I/O	I, M	P2[1]	Direct switched capacitor block input.	57	I/O	M	P3[2]
8	I/O	M	P4[7]		58	I/O	M	P3[4]
9	I/O	M	P4[5]		59	I/O	M	P3[6]
10	I/O	M	P4[3]		60			HCLK	OCD high-speed clock output.
11	I/O	M	P4[1]		61			CCLK	OCD CPU clock output.
12			OCDE	OCD even data I/O.	62	Input		XRES	Active high pin reset with internal pull down.
13			OCDO	OCD odd data output.	63	I/O	M	P4[0]
14			NC	No connection.	64	I/O	M	P4[2]
15	Power		Vss	Ground connection.	65	Power		Vss	Ground connection.
16	I/O	M	P3[7]		66	I/O	M	P4[4]
17	I/O	M	P3[5]		67	I/O	M	P4[6]
18	I/O	M	P3[3]		68	I/O	I, M	P2[0]	Direct switched capacitor block input.
19	I/O	M	P3[1]		69	I/O	I, M	P2[2]	Direct switched capacitor block input.
20	I/O	M	P5[7]		70	I/O		P2[4]	External Analog Ground (AGND) input.
21	I/O	M	P5[5]		71			NC	No connection.
22	I/O	M	P5[3]		72	I/O		P2[6]	External Voltage Reference (VREF) input.
23	I/O	M	P5[1]		73			NC	No connection.
24	I/O	M	P1[7]	I2C Serial Clock (SCL).	74	I/O	I	P0[0]	Analog column mux input.
25			NC	No connection.	75			NC	No connection.
26			NC	No connection.	76			NC	No connection.
27			NC	No connection.	77	I/O	I, M	P0[2]	Analog column mux input and column output.
28	I/O		P1[5]	I2C Serial Data (SDA)	78			NC	No connection.
29	I/O		P1[3]		79	I/O	I, M	P0[4]	Analog column mux input and column output.
30	I/O		P1[1]	Crystal (XTALin), I2C Serial Clock (SCL),	80			NC	No connection.
				ISSP SCLK[1].
31			NC	No connection.	81	I/O	I, M	P0[6]	Analog column mux input.
32	Power		Vss	Ground connection.	82	Power		Vdd	Supply voltage.
33	USB		D+		83			NC	No connection.
34	USB		D-		84	Power		Vss	Ground connection.
35	Power		Vdd	Supply voltage.	85			NC	No connection.
36	I/O		P7[7]		86			NC	No connection.
37	I/O		P7[6]		87			NC	No connection.
38	I/O		P7[5]		88			NC	No connection.
39	I/O		P7[4]		89			NC	No connection.
40	I/O		P7[3]		90			NC	No connection.
41	I/O		P7[2]		91			NC	No connection.
42	I/O		P7[1]		92			NC	No connection.
43	I/O		P7[0]		93			NC	No connection.
44			NC	No connection.	94			NC	No connection.
45			NC	No connection.	95	I/O	I, M	P0[7]	Analog column mux input.
46			NC	No connection.	96			NC	No connection.
47			NC	No connection.	97	I/O	I/O,	P0[5]	Analog column mux input and column output.
							M
48	I/O		P1[0]	Crystal (XTALout), I2C Serial Data (SDA),	98			NC	No connection.
				ISSP SDATA[1].
49	I/O		P1[2]		99	I/O	I/O,	P0[3]	Analog column mux input and column output.
							M
50	I/O		P1[4]	Optional External Clock Input (EXTCLK).	100			NC	No connection.

Document Number: 38-12018 Rev. *M Page 15 of 47

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