CY8C24094, CY8C24794
CY8C24894, CY8C24994
Document Number: 38-12018 Rev. *M Page 36 of 47
10.0.5 AC Programming Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 10-25. 3.3V AC Analog Output Buffer Specifications
Symbol Description Min Typ Max Units Notes
TROB Rising Settling Time to 0.1%, 1V Step, 100 pF
Load
Power = Low
Power = High
–
–
–
–
3.8
3.8
μs
μs
TSOB Falling Settling Time to 0.1%, 1V Step, 100 pF
Load
Power = Low
Power = High
–
–
–
–
2.6
2.6 μs
μs
SRROB Rising Slew Rate (20% to 80%), 1V Step, 100
pF Load
Power = Low
Power = High
0.5
0.5
–
–
–
–
V/μs
V/μs
SRFOB Falling Slew Rate (80% to 20%), 1V Step, 100
pF Load
Power = Low
Power = High
0.5
0.5
–
–
–
–
V/μs
V/μs
BWOBSS Small Signal Bandwidth, 20mVpp, 3dB BW,
100 pF Load
Power = Low
Power = High
0.7
0.7
–
–
–
–
MHz
MHz
BWOBLS Large Signal Bandwidth, 1Vpp, 3dB BW, 100
pF Load
Power = Low
Power = High
200
200
–
–
–
–
kHz
kHz
Table 10-26. AC Programming Specifications
Symbol Description Min Typ Max Units Notes
TRSCLK Rise Time of SCLK 1 – 20 ns
TFSCLK Fall Time of SCLK 1 – 20 ns
TSSCLK Data Set up Time to Falling Edge of SCLK 40 ––ns
THSCLK Data Hold Time from Falling Edge of SCLK 40 ––ns
FSCLK Frequency of SCLK 0–8MHz
TERASEB Flash Erase Time (Block) –10 –ms
TWRITE Flash Block Write Time –30 –ms
TDSCLK Data Out Delay from Falling Edge of SCLK – – 45 ns Vdd > 3.6
TDSCLK3 Data Out Delay from Falling Edge of SCLK – – 50 ns 3.0 ≤ Vdd ≤ 3.6
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