CY8C24094, CY8C24794
CY8C24894, CY8C24994
Document Number: 38-12018 Rev. *M Page 34 of 47
10.0.1 AC Low Power Comparator Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C TA 85°C, 3.0V to 3.6V and -40°C TA 85°C, or 2.4V to 3.0V and -40°C TA 85°C, respectively. Typical parameters
apply to 5V at 25°C and are for design guidance only.
10.0.2 AC Digital Block Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C TA 85°C, or 3.0V to 3.6V and -40°C TA 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 10-21. AC Low Power Comparator Specifications
Symbol Description Min Typ Max Units Notes
TRLPC LPC response time 50 μs 50 mV overdrive comparator
reference set within VREFLPC.
Table 10-22. AC Digital Block Specifications
Function Description Min Typ Max Units Notes
Timer Capture Pulse Width 50[13] – – ns
Maximum Frequency, No Capture – – 49.92 MHz 4.75V < Vdd < 5.25V.
Maximum Frequency, With Capture – – 25.92 MHz
Counter Enable Pulse Width 50[13] – – ns
Maximum Frequency, No Enable Input – – 49.92 MHz 4.75V < Vdd < 5.25V.
Maximum Frequency, Enable Input – – 25.92 MHz
Dead
Band
Kill Pulse Width:
Asynchronous Restart Mode 20 – – ns
Synchronous Restart Mode 50[13] – – ns
Disable Mode 50[13] – – ns
Maximum Frequency – – 49.92 MHz 4.75V < Vdd < 5.25V.
CRCPRS
(PRS
Mode)
Maximum Input Clock Frequency – – 49.92 MHz 4.75V < Vdd < 5.25V.
CRCPRS
(CRC
Mode)
Maximum Input Clock Frequency – – 24.6 MHz
SPIM Maximum Input Clock Frequency – – 8.2 MHz Maximum data rate at 4.1 MHz due
to 2 x over clocking.
SPIS Maximum Input Clock Frequency – – 4.1 MHz
Width of SS_ Negated Between Transmissions 50[13] – – ns
Trans-
mitter
Maximum Input Clock Frequency – – 24.6 MHz Maximum data rate at 3.08 MHz
due to 8 x over clocking.
Receiver Maximum Input Clock Frequency – – 24.6 MHz Maximum data rate at 3.08 MHz
due to 8 x over clocking.
Note
13.50 ns minimum input pulse width is based on the input synchronizers running at 24 MHz (42 ns nominal period).
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