Cypress CY8C24094, CY8C24894, CY8C24994 SDA SCL SSr SP, T, T T T T, T, T T, T

CY8C24094, CY8C24794
CY8C24894, CY8C24994
Document Number: 38-12018 Rev. *M Page 37 of 47
10.0.6 AC I2C Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Figure 10-6. Definition for Timing for Fast/Standard Mode on the I2C Bus
Table 10-27. AC Characteristics of the I2C SDA and SCL Pins for Vdd
Symbol Description Standard Mode Fast Mode Units Notes
Min Max Min Max
FSCLI2C SCL Clock Frequency 0 100 0 400 kHz
THDSTAI2
C
Hold Time (repeated) START Condition. After
this period, the first clock pulse is generated.
4.0 –0.6–μs
TLOWI2C LOW Period of the SCL Clock 4.7 –1.3–μs
THIGHI2C HIGH Period of the SCL Clock 4.0 –0.6–μs
TSUSTAI2
C
Set-up Time for a Repeated START Condition 4.7 –0.6–μs
THDDATI2
C
Data Hold Time 0 –0–μs
TSUDATI2
C
Data Set-up Time 250 –100
[14] –ns
TSUSTOI2
C
Set-up Time for STOP Condition 4.0 –0.6–μs
TBUFI2C Bus Free Time Between a STOP and START
Condition
4.7 –1.3–μs
TSPI2C Pulse Width of spikes are suppressed by the
input filter.
–– 0 50 ns
SDA
SCL
SSr SP
TBUFI2C
TSPI2C
THDSTAI2C
TSUSTOI2C
TSUSTAI2C
TLOWI2C
THIGHI2C
THDDATI2C
THDSTAI2C
TSUDATI2C
Note
14.A Fast-Mode I2C-bus device can be used in a Standard-Mode I2C-bus system, but the requirement tSU;DAT Š 250 ns must then be met. This automatically is the case
if the device does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next data bit to the
SDA line trmax + tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard-Mode I2C-bus specification) before the SCL line is released.
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