CYS25G0101DX-ATC Evaluation Board User’s Guide
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J5 SD This jumper is used to set the SD signal. When open (default), SD signal will be driven by the
optical module. When 1-2 are shorted, SD is forced to HIGH. When 2-3 are shorted, SD is
forced to LOW. Figure 3 shows the orientation of this jumper
J6 TEST0 This jumper, when shorted, is to enable the Parallel Line Loopback mode.
J7 LFI Test Tap for CYS25G0101DX’s LFI (pin 1). Figure 3 shows the orientation of this jumper
J8 FIFO_ERR Test Tap for CYS25G0101DX’s LIFO (pin 51). Figure 3 shows the orientation of this jumper
SMA10 TXCLKI Optional SMA connector for CYS25G0101DX’s TXCLKI (pin 57). R37 need to be popu-
lated, if this connector is used
SMA11 RXCLK Optional SMA connector for CYS25G0101DX’s RXCLK (pin 24). C118, R118, R138 and
R158 need to be populated and C116, R116, and R136 need to be unpopulated, if
this connector is used
SMA12 TXCLKO Optional SMA connector for CYS25G0101DX’s TXCLKO (pin 79). C119, R119, R139 and
R159 need to be populated and C117, R117, and R137 need to be unpopulated, if
this connector is used
SMA13 IN+ SMA connector for CYS25G0101DX’s IN+ (pin 109). This connector is also for the optional
optical module interface
SMA14 IN- SMA connector for CYS25G0101DX’s IN– (pin 108). This connector is also for the optional
optical module interface
SMA15 OUT- SMA connector for CYS25G0101DX’s OUT– (pin 104). This connector is also for the option-
al optical module interface
SMA16 OUT+ SMA connector for CYS25G0101DX’s OUT+ (pin 103). This connector is also for the option-
al optical module interface
SMA17 REFCLKP Optional SMA connector for CYS25G0101DX’s REFCLK+ (pin 87). This connector is for us-
ing the external reference clock instead of using the “on-board” oscillator (155.52MHz). To
use the external reference clock, C400 and C401 (0.01-µF cap) have to be removed
and placed on C402 and C403 positions. Also, The CLKVCC, P2, has to be discon-
nected from the power supply
SMA18 REFCLKN Optional SMA connector for CYS25G0101DX’s REFCLK+ (pin 87). This connector is for us-
ing the external reference clock instead of using the “on-board” oscillator (155.52MHz). To
use the external reference clock, C400 and C401 (0.01-µF cap) have to be removed
and placed on C402 and C403 positions. Also, The CLKVCC, P2, has to be discon-
nected from the power supply
P1 GND Power Ground. For external power supply
P2 CLKVCC Power supply - +3.3V for the clock oscillator
P3 VDDQ Power supply - +3.3V for LVPECL output. +1.5V for HSTL outputs
P4 VCC_OPTIC Power supply - +3.3V for the optional optical module
P5 VCC Power supply - +3.3V for digital and low-speed I/O function
P6 V_Par Power supply - +3.3V for LVPECL output. +1.5V for HSTL outputs
Table 2. Pin Assignment of J1 Header and Description of J10 Header
Pin Number Name I/O Characteristics Description
1 RXD15 HSTL output Parallel receive data output RXD15. The outputs change following
RXCLK↓
3 RXD14 HSTL output Parallel receive data output RXD14. The outputs change following
RXCLK↓
Table 1. Functional Description of the Connectors (continued)
Jumpers and
Connectors Name Description
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