Cypress CYS25G0101DX-ATC - page 5

CYS25G0101DX-ATC Evaluation Board User’s Guide

5

Figure 1. The Block Diagram of the CYS25G0101DX

TXD

15:0

TX PLL

x16

/16

RXD

15:0

(155.52MHz)

REFCLK

(155.52MHz)

RXCLKOUT

SHIFTER RX CDR

PLL

TXCLKO

Input

Register

Output

Register

FIFO

(5byte)

SHIFTER

(155.52MHz)

TXCLKI

/16

DIAGLOOP

LINELOOP

LOOPA

IN±

OUT±

Lock-to-Data /

Clock Control

Logic

LOOPTIME

FIFO_RST FIFO_ERR

RESETLFISDLOCKREFPWRDN

Retimed

Data

Recovered

Bit-Clock

Lock-to-Ref

Tx Bit-Clock

[+] Feedback

Contents

Main Page Page 1. Introduction 2. Features 3. Kit Contents 4. Functional Description Page Page Page Page Page CYS25G0101DX-ATC Evaluation Board Users Guide 11 Figure 3. The Jumper Orientations of the CYS25G0101DX 5. Diagnostic Modes 5.1 Diagnostic Loopback Mode 5.2 Line Loopback Page 5.4 Parallel Line Loopback (TEST0) Mode 5.4.1 Test the Internal RX CDR PLL Only 5.4.2 Test the Internal RX CDR PLL and TX PLL 6. Testing Hookup 6.1 Set-up for BERT Test 6.2 Set-up for Eye Diagram Test 6.3 SONET Jitter Transfer and Jitter Tolerance Test 6.4 Set-up for Testing the TX PLL in Parallel Line Loopback Mode Page Page Page 10. Schematic Diagram, PCB Layout and BOM (Bill of Material)