Cypress CYS25G0101DX-ATC

CYS25G0101DX-ATC Evaluation Board User’s Guide

Table of Contents

1. Introduction ....................................................................................................................................... 4

2. Features ............................................................................................................................................. 4

3. Kit Contents ...................................................................................................................................... 4

4. Functional Description ..................................................................................................................... 4

5. Diagnostic Modes ........................................................................................................................... 12

5.1 Diagnostic Loopback Mode ..................................................................................................... 12

5.2 Line Loopback ...........................................................................................................................13

5.3 Analog Line Loopback ..............................................................................................................14

5.4 “Parallel Line Loopback” (TEST0) Mode ................................................................................ 15

5.4.1 Test the Internal RX CDR PLL Only ................................................................................ 15

5.4.2 Test the Internal RX CDR PLL and TX PLL .................................................................... 15

6. Testing Hookup ............................................................................................................................... 16

6.1 Set-up for BERT Test ................................................................................................................ 16

6.2 Set-up for Eye Diagram Test ....................................................................................................17

6.3 SONET Jitter Transfer and Jitter Tolerance Test ................................................................... 18

6.4 Set-up for Testing the TX PLL in Parallel Line Loopback Mode ...........................................19

7. Eye Diagram Testing Result .......................................................................................................... 20

8. Jitter Transfer Testing Result ........................................................................................................ 21

9. Jitter Tolerance Testing Result ..................................................................................................... 22

10. Schematic Diagram, PCB Layout and BOM (Bill of Material) ................................................... 23

Appendix A: Schematic Diagrams of the CYS25G0101DX Evaluation Board ............................... 24

Appendix B: PCB Layout Diagrams of the CYS25G0101DX Evaluation Board ............................ 32

Appendix C: CYS25G0101DX Evaluation Board LVPECL BOM (Bill of Material) ......................... 42

Appendix D: CYS25G0101DX Evaluation Board HSTL BOM (Bill of Material) .............................. 47

List of Figures

Figure 1. The Block Diagram of the CYS25G0101DX ......................................................................... 5

Figure 2. The CYS25G0101DX Evaluation Board ................................................................................6

Figure 3. The Jumper Orientations of the CYS25G0101DX ............................................................. 11

Figure 4. Diagnostic Loopback Mode Data Path ..............................................................................12

Figure 5. Line Loopback Mode Data Path .........................................................................................13

Figure 6. Analog Line Loopback Mode Data Path ............................................................................ 14

Figure 7. Parallel Loopback (TEST0) Mode Data Path .....................................................................15

Figure 8. Equipment Set-up for BERT Test .......................................................................................16

Figure 9. Equipment Set-up For Eye Diagram Test .......................................................................... 17

Figure 10. Equipment Set-up For Jitter Test ..................................................................................... 18

Figure 11. Equipment Set-up For Testing the TX PLL in Parallel Line Loopback Mode ............... 19

Figure 12. CYS25G0101DX Evaluation Board Eye Diagram ............................................................ 20

Figure 13. CYS25G0101DX Evaluation Board GR-253 Jitter Transfer Testing Result ..................21

Figure 14. CYS25G0101DX Evaluation Board G958 Jitter Transfer Testing Result ...................... 21

Figure 15. CYS25G0101DX Evaluation Board GR-253 JitterTolerance Testing Result ................. 22

Figure 16. CYS25G0101DX Evaluation Board G825 Jitter Tolerance Testing Result ....................22

Figure 17. Top Level of CYS25G0101DX Evaluation Board Schematic Diagram .........................25

Figure 18. Parallel Output Block Schematic Diagram ...................................................................... 26

Figure 19. Parallel Input Block Schematic Diagram ......................................................................... 27

Figure 20. Signals Block Schematic Diagram ...................................................................................28

Figure 21. Power Supply Block Schematic Diagram ........................................................................ 29

Figure 22. Control Block Schematic Diagram ................................................................................... 30

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