Intel Microcontroller Device Features, Block Diagram, Features of the 8XC196NP and 80C196NU, Rom

8XC196NP, 80C196NU USER’S MANUAL

2.2DEVICE FEATURES

Table 2-1 lists the features of the 8XC196NP and 80C196NU.

Table 2-1. Features of the 8XC196NP and 80C196NU

		ROM	Register	I/O Pins	EPA	SIO	PWM	Chip-	External
Device	Pins		RAM					select	Interrupt
		(Note 1)		(Note 3)	Pins	Ports	Channels
			(Note 2)					Pins	Pins
8XC196NP	100	4 K	1024	64	4	1	3	6	4
80C196NU	100	0	1024	64	4	1	3	6	4

NOTES:

1.Nonvolatile memory is optional for the 8XC196NP, but is not available for the 80C196NU. The second character of the device name indicates the presence and type of nonvolatile memory. 80C196NP = none; 83C196NP = ROM.

2.Register RAM amounts include the 24 bytes allocated to core special-function registers (SFRs) and the stack pointer.

3.I/O pins include address, data, and bus control pins and 32 I/O port pins.

2.3BLOCK DIAGRAM

Figure 2-1 shows the major blocks within the device. The core of the device (Figure 2-2) consists of the central processing unit (CPU) and memory controller. The CPU contains the register file and the register arithmetic-logic unit (RALU). The CPU connects to both the memory controller and an interrupt controller via a 16-bit internal bus. An extension of this bus connects the CPU to the internal peripheral modules. In addition, an 8-bit internal bus transfers instruction bytes from the memory controller to the instruction register in the RALU.

Core

Clock and

Power Mgmt.

Optional

ROM

Interrupt

Controller

PTS

I/O SIO PWM EPA

A2801-01

Figure 2-1. 8XC196NP and 80C196NU Block Diagram

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