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Intel 80C196NU, 8XC196NP Ebmovi Extended Interruptable Block PTRS, Cntreg, Count ← Cntreg, Ebr

Models: Microcontroller 80C196NU 8XC196NP

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8XC196NP, 80C196NU USER’S MANUAL

Table A-6. Instruction Set (Continued)

Mnemonic

 

 

 

Operation

 

 

 

 

Instruction Format

 

 

 

 

 

EBMOVI

EXTENDED INTERRUPTABLE BLOCK

 

PTRS, CNTREG

 

MOVE. Moves a block of word data from one

EBMOVI

prt2_reg, wreg

 

memory location to another. This instruction

 

(11100100) (wreg) (prt2_reg)

 

allows you to move blocks of up to 64K words

 

 

 

 

between any two locations in the 16-Mbyte

 

 

 

address space. This instruction is inter-

NOTES:

The pointers are autoincre-

 

ruptable.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

mented during this instruction.

 

 

 

 

 

 

 

 

 

 

 

 

 

The source and destination addresses are

 

However, CNTREG is decre-

 

calculated using the extended indirect with

 

mented only when the instruc-

 

autoincrement addressing mode. A quad-

 

tion is interrupted. When

 

word register (PTRS) addresses the 24-bit

 

EBMOVI is interrupted,

 

source and destination pointers, which are

 

CNTREG is updated to store

 

stored in adjacent double-word registers. The

 

the interim word count at the

 

source pointer (SRCPTR) is the low double-

 

time of the interrupt. For this

 

word and the destination pointer is the high

 

reason, you should always

 

double-word of PTRS. A word register

 

reload CNTREG before starting

 

(CNTREG) specifies the number of transfers.

 

an EBMOVI.

 

The blocks of data can reside anywhere in

 

For 20-bit addresses, the offset

 

memory, but should not overlap.

 

 

 

 

COUNT ← (CNTREG)

 

 

 

 

 

 

must be in the range of

 

LOOP: SRCPTR ← (PTRS)

 

 

 

 

+524287 to –524288.

 

DSTPTR ← (PTRS + 2)

 

 

 

 

 

 

 

 

(DSTPTR) ← (SRCPTR)

 

 

 

 

 

 

(PTRS) ← SRCPTR + 2

 

 

 

 

 

 

 

 

(PTRS + 2)

← DSTPTR + 2

 

 

 

 

 

 

COUNT ← COUNT 1

 

 

 

 

 

 

 

 

if COUNT ≠ 0 then

 

 

 

 

 

 

 

 

go to LOOP

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PSW Flag Settings

 

 

 

 

 

 

Z

N

C

 

V

 

VT

ST

 

 

 

 

 

—

—

— —

—

—

 

 

 

 

 

 

 

 

 

EBR

EXTENDED BRANCH INDIRECT. Continues

 

DEST

 

execution at the address specified in the

EBR

cadd

 

operand word register. This instruction is an

 

or

 

 

unconditional indirect jump to anywhere in

 

 

 

 

 

the 16-Mbyte address space.

 

 

 

EBR

[treg]

 

EBR shares its opcode (E3) with the BR

(11100011) (treg)

 

instruction. To differentiate between the two,

 

 

 

the compiler sets the least-significant bit of

NOTE: For 20-bit addresses, the offset

 

the EBR instruction. For example: EBR [50]

 

 

must be in the range of +524287

 

becomes E351 when compiled.

 

 

 

 

 

 

 

to –524288.

 

PC ← (DEST)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PSW Flag Settings

 

 

 

 

 

 

Z

N

C

 

V

 

VT

ST

 

 

 

 

 

—

—

— —

 

—

 

—

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A-16

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Intel 80C196NU, 8XC196NP, Microcontroller manual Ebmovi Extended Interruptable Block PTRS, Cntreg, Count ← Cntreg, Ebr
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Microcontroller, 80C196NU, 8XC196NP specifications

The Intel 8XC196NP and 80C196NU microcontrollers are part of Intel's renowned 16-bit microcontroller series that gained popularity in the 1980s and 1990s for embedded systems applications. Designed for a variety of applications, these microcontrollers are characterized by their robust performance, versatility, and industry-standard architecture.

The 8XC196NP features an enhanced instruction set with over 100 instructions, allowing for efficient code execution. It operates at clock speeds up to 16 MHz, which contributes to improved performance in time-sensitive applications. The microcontroller is equipped with a 16-bit data bus, enabling more efficient data handling compared to its 8-bit predecessors, thus accommodating complex algorithms and large data sets.

In terms of memory architecture, the 8XC196NP supports an addressable memory space of up to 64 KB of program memory and 64 KB of data memory. This configuration provides sufficient space for large applications while ensuring fast data access. The microcontroller includes integrated features such as timers, serial I/O capabilities, and interrupt processing, which enhance its functionality for real-time applications and control mechanisms.

The 80C196NU, on the other hand, is designed for lower power operation, making it suitable for battery-powered devices. This microcontroller maintains similar features to the 8XC196NP while offering advancements that support low-power consumption. The 80C196NU can also function in a range of temperature environments, making it adaptable for industrial applications.

Both the 8XC196NP and 80C196NU support external memory interfacing, allowing designers to expand the system's capability by connecting additional ROM and RAM. This flexibility makes them appealing for developing complex systems, such as motor controls, industrial automation, and consumer electronics.

Another standout feature of these microcontrollers is their built-in debugging capabilities. Intel provided hardware and software tools that enabled developers to test and troubleshoot their applications effectively, reducing the development time and increasing reliability.

Overall, the Intel 8XC196NP and 80C196NU microcontrollers stand out for their dependability, versatility, and performance, contributing significantly to the evolution of embedded system design. Their legacy continues to influence modern microcontroller technology, ensuring their relevance in a wide array of applications today.