Intel 80C196NU, 8XC196NP, Microcontroller manual Sram, Uart, Chip Contents, Buscon, C0H

INTERFACING WITH EXTERNAL MEMORY

8XC196

CS0#

CS2#

A19:0

AD15:0

RD#

WR#

CS1#

		Flash		SRAM
	256K×￿16			8K×￿8
	CE#
			CE#
A18:1	A17:0		A12:0
			A12:0
AD15:0	D15:0		AD7:0
			D7:0
		0 WS		0 WS
	80000–FFFFFH		7E000–7FFFFH
	OE#	WE#	OE#	WE#
A2:0	A2:0	82510
		UART	Rxd
AD7:0	D7:0		Txd

3WS

CE# 01E00–01EFFH

A2433-03

Figure 13-5. Example System for Setting Up Chip-select Outputs

Table 13-8. BUSCONx Registers for the Example System

Chip-				Contents of
select	Multiplexing	Bus Width	Wait States
				BUSCONx
Output
0	Demultiplexed	16 bits	0	C0H
1	Demultiplexed	8 bits	3	83H
2	Demultiplexed	8 bits	0	80H

The location and size of an address range are specified by the ADDRCOMx register and the ADDRMSKx register (see Figure 13-2 and Figure 13-3). The 8-Kbyte SRAM is assigned to ad- dress range 7E000–7FFFFH and uses chip-select output 2. The 12 most-significant bits of the base address (7E000H) are written to the BASE19:8 bits in the ADDRCOM2 register, which then contains 07E0H.

The address range for CS2# is 8 Kbytes or 213 bytes (n = 13). The number of bits to be set in MASK19:8 of ADDRMSK2 is 20 – n = 7. After the 7 most-significant bits of MASK19:8 are set, ADDRMSK2 contains 0FE0H. Results for CS0# and CS1# are found similarly (see Table 13-9).

13-13