Intel 80C196NU, 8XC196NP manual Controlling Wait States, Bus Width, and Bus Multiplexing, WS1 WS0

8XC196NP, 80C196NU USER’S MANUAL

Note that the 32-Kbyte address range could not have 4000H as base address, for example, because 4000H is not on a 32-Kbyte boundary.

“Example of a Chip-select Setup” on page 13-12 shows another example of setting up the chip- select unit.

13.3.2 Controlling Wait States, Bus Width, and Bus Multiplexing

For each chip-select output address range, the bus control register BUSCONx (Figure 13-4)de- termines the wait states, the bus width, and the address/data multiplexing.

BUSCONx	Address:	Table 13-7
x = 0–5	Reset State:

For the address range assigned to chip-select x, the bus control (BUSCONx) register specifies the number of wait states, the bus width, and the address/data multiplexing for all external bus cycles that access address range x.

7

DEMUX BW16 — —

0

— — WS1 WS0

Bit	Bit			Function
Number	Mnemonic
7	DEMUX	Address/Data Multiplexing
		This bit specifies the address/data multiplexing on AD15:0 for all
		external accesses to the address range assigned to chip-select x output.
		0	= multiplexed
		1	= demultiplexed
6	BW16	Bus Width
		This bit specifies the bus width for all external accesses to the address
		range assigned to chip-select x output.
		0	= 8 bits
		1	= 16 bits
5:2	—	Reserved; for compatibility with future devices, write zeros to these bits.
1:0	WS1:0	Wait States
		These bits specify the number of wait states for all external accesses to
		the address range assigned to chip-select x output.
		WS1 WS0		Wait States
		0	0	0
		0	1	1
		1	0	2
		1	1	3

Figure 13-4. Bus Control (BUSCONx) Register

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