Intel 80C196NU, 8XC196NP manual Signal Descriptions, Table B-2. Description of Columns of Table B-3

8XC196NP, 80C196NU USER’S MANUAL

B.2 SIGNAL DESCRIPTIONS

Table B-2 defines the columns used in Table B-3, which describes the signals.

	Table B-2. Description of Columns of Table B-3
Column Heading		Description
Name		Lists the signals, arranged alphabetically. Many pins have two functions, so
		there are more entries in this column than there are pins. Every signal is
		listed in this column.
Type		Identifies the pin function listed in the Name column as an input (I), output
		(O), bidirectional (I/O), power (PWR), or ground (GND).
		Note that all inputs except RESET# are sampled inputs. RESET# is a level-
		sensitive input. During powerdown mode, the powerdown circuitry uses
		EXTINTx as a level-sensitive input.
Description		Briefly describes the function of the pin for the specific signal listed in the
		Name column. Also lists the alternate fuction that are multiplexed with the
		signal (if applicable).

		Table B-3. Signal Descriptions
Name	Type	Description
A15:0	I/O	System Address Bus
		These address lines provide address bits 0–15 during the entire external
		memory cycle during both multiplexed and demultiplexed bus modes.
A19:16	I/O	Address Lines 16–19
		These address lines provide address bits 16–19 during the entire external
		memory cycle, supporting extended addressing of the 1 Mbyte address space.
		NOTE: Internally, there are 24 address bits; however, only 20 address lines
		(A19:0) are bonded out. The internal address space is 16 Mbytes
		(000000–FFFFFFH) and the external address space is 1 Mbyte
		(00000–FFFFFH). The device resets to FF2080H in internal ROM or
		F2080H in external memory.
		A19:16 are multiplexed with EPORT.3:0.
AD15:0	I/O	Address/Data Lines
		The function of these pins depend on the bus size and mode. When a bus
		access is not occurring, these pins revert to their I/O port function.
		16-bit Multiplexed Bus Mode:
		AD15:0 drive address bits 0–15 during the first half of the bus cycle and drives
		or receives data during the second half of the bus cycle.
		8-bit Multiplexed Bus Mode:
		AD15:8 drive address bits 8–15 during the entire bus cycle. AD7:0 drive
		address bits 0–7 during the first half of the bus cycle and either drive or receive
		data during the second half of the bus cycle.
		16-bit Demultiplexed Mode:
		AD15:0 drive or receive data during the entire bus cycle.
		8-bit Demultiplexed Mode:
		AD7:0 drive or receive data during the entire bus cycle. AD15:8 drive the data
		that is currently on the high byte of the internal bus.

B-6