REGISTERS

PSW

PSW (Continued)

no direct access

The processor status word (PSW) actually consists of two bytes. The high byte is the status word, which is described here; the low byte is the INT_MASK register. The status word contains one bit (PSW.1) that globally enables or disables servicing of all maskable interrupts, one bit (PSW.2) that enables or disables the peripheral transaction server (PTS), and six Boolean flags that reflect the state of a user’s program.

The status word portion of the PSW cannot be accessed directly. To access the status word, push the value onto the stack (PUSHF), then pop the value to a register (POP test_reg). The PUSHF and PUSHA instructions save the PSW in the system stack and then clear it; POPF and POPA restore it.

15

Z

N

V

VT

 

 

 

 

7

8

C

PSE

I

ST

 

 

 

 

0

 

 

 

See INT_MASK on page C-25

 

 

 

 

 

 

 

Bit

Bit

Function

 

 

Number

Mnemonic

 

 

 

 

 

 

 

 

 

 

4

VT

Overflow-trap Flag

 

 

 

 

This flag is set when the overflow flag is set, but it is cleared only by the

 

 

 

 

CLRVT, JVT, and JNVT instructions. This allows testing for a possible

 

 

 

 

overflow at the end of a sequence of related arithmetic operations, which

 

 

 

 

is generally more efficient than testing the overflow flag after each

 

 

 

 

operation.

 

 

 

 

 

 

 

3

C

Carry Flag

 

 

 

 

This flag is set to indicate an arithmetic carry or the last bit shifted out of

 

 

 

 

an operand. It is cleared if a subtraction operation generates a borrow.

 

 

 

 

Normally, the result is rounded up if the carry flag is set. The sticky bit

 

 

 

 

flag allows a finer resolution in the rounding decision. (See the PSW flag

 

 

 

 

descriptions in Appendix A for details.)

 

 

 

 

 

 

 

2

PSE

PTS Enable

 

 

 

 

This bit globally enables or disables the peripheral transaction server

 

 

 

 

(PTS). The EPTS instruction sets this bit; DPTS clears it.

 

 

 

 

1 = enable PTS

 

 

 

 

0 = disable PTS

 

 

 

 

 

 

 

1

I

Interrupt Disable (Global)

 

 

 

 

This bit globally enables or disables the servicing of all maskable

 

 

 

 

interrupts. The bits in INT_MASK and INT_MASK1 individually enable or

 

 

 

 

disable the interrupts. The EI instruction sets this bit; DI clears it.

 

 

 

 

1 = enable interrupt servicing

 

 

 

 

0 = disable interrupt servicing

 

 

 

 

 

 

 

0

ST

Sticky Bit Flag

 

 

 

 

This flag is set to indicate that, during a right shift, a “1” was sh ifted into

 

 

 

 

the carry flag and then shifted out. It can be used with the carry flag to

 

 

 

 

allow finer resolution in rounding decisions.

 

 

 

 

 

 

 

 

 

 

 

C-35

Page 425 Page 427
Page 426
Image 426
Intel 80C196NU, 8XC196NP, Microcontroller manual Psw, Bit Function Number Mnemonic
Page 425 Page 427

Microcontroller, 80C196NU, 8XC196NP specifications

The Intel 8XC196NP and 80C196NU microcontrollers are part of Intel's renowned 16-bit microcontroller series that gained popularity in the 1980s and 1990s for embedded systems applications. Designed for a variety of applications, these microcontrollers are characterized by their robust performance, versatility, and industry-standard architecture.

The 8XC196NP features an enhanced instruction set with over 100 instructions, allowing for efficient code execution. It operates at clock speeds up to 16 MHz, which contributes to improved performance in time-sensitive applications. The microcontroller is equipped with a 16-bit data bus, enabling more efficient data handling compared to its 8-bit predecessors, thus accommodating complex algorithms and large data sets.

In terms of memory architecture, the 8XC196NP supports an addressable memory space of up to 64 KB of program memory and 64 KB of data memory. This configuration provides sufficient space for large applications while ensuring fast data access. The microcontroller includes integrated features such as timers, serial I/O capabilities, and interrupt processing, which enhance its functionality for real-time applications and control mechanisms.

The 80C196NU, on the other hand, is designed for lower power operation, making it suitable for battery-powered devices. This microcontroller maintains similar features to the 8XC196NP while offering advancements that support low-power consumption. The 80C196NU can also function in a range of temperature environments, making it adaptable for industrial applications.

Both the 8XC196NP and 80C196NU support external memory interfacing, allowing designers to expand the system's capability by connecting additional ROM and RAM. This flexibility makes them appealing for developing complex systems, such as motor controls, industrial automation, and consumer electronics.

Another standout feature of these microcontrollers is their built-in debugging capabilities. Intel provided hardware and software tools that enabled developers to test and troubleshoot their applications effectively, reducing the development time and increasing reliability.

Overall, the Intel 8XC196NP and 80C196NU microcontrollers stand out for their dependability, versatility, and performance, contributing significantly to the evolution of embedded system design. Their legacy continues to influence modern microcontroller technology, ensuring their relevance in a wide array of applications today.
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