Intel Microcontroller manual PTS Single Transfer Mode Control Block, Register Location Function

STANDARD AND PTS INTERRUPTS

PTS Single Transfer Mode Control Block

In single transfer mode, the PTS control block contains a source and destination address (PTSSRC and PTSDST), a control register (PTSCON), and a transfer count (PTSCOUNT).

Unused

Unused

PTSDST (HI)

PTSDST (LO)

PTSSRC (HI)

PTSSRC (LO)

PTSCON

PTSCOUNT

7								0
0	0	0		0	0	0	0	0
7								0
0	0	0		0	0	0	0	0
15								8
		PTS Destination Address (high byte)
7								0
		PTS Destination Address (low byte)
15								8
			PTS Source Address (high byte)
7								0
			PTS Source Address (low byte)
7								0
M2	M1	M0		BW	SU	DU	SI	DI
7								0
		Consecutive Byte or Word Transfers

Register	Location	Function
PTSDST	PTSCB + 4	PTS Destination Address
		Write the destination memory location to this register. A valid address is
		any unreserved memory location within page 00H; however, it must
		point to an even address if word transfers are selected.
PTSSRC	PTSCB + 2	PTS Source Address
		Write the source memory location to this register. A valid address is any
		unreserved memory location within page 00H; however, it must point to
		an even address if word transfers are selected.

Figure 6-12. PTS Control Block — Single Transfer Mode

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