Intel Microcontroller, 80C196NU manual Explanation of AC Symbols, AC Timing Definitions, Conditions

8XC196NP, 80C196NU USER’S MANUAL

13.9.2 Explanation of AC Symbols

Each symbol consists of two pairs of letters prefixed by “T” (for time). The characters in a pair indicate a signal and its condition, respectively. Symbols represent the time between the two sig- nal/condition points. For example, TLLRL is the time between signal L (ALE) condition L (Low) and signal R (RD#) condition L (Low). Table 13-15 defines the signal and condition codes.

Table 13-15. AC Timing Symbol Definitions

Signals

A†	Address	H	HOLD#	S	CSx#
B	BHE#	HA	HLDA#	W	WR#, WRH#, WRL#
C	CLKOUT	L	ALE	X	XTAL1
D	Data	Q	Data Out	Y	READY
G	Buswidth	R	RD#

†Address bus (demultiplexed mode) or address/data bus (multiplexed mode)

Conditions

H High

L Low

V Valid

XNo Longer Valid

Z Floating

13.9.3 AC Timing Definitions

Table 13-16 defines the AC timing specifications that the memory system must meet and those that the device will provide.

	Table 13-16. AC Timing Definitions
Symbol	Definition
	The External Memory System Must Meet These Specifications
TAVDV	Address Valid to Input Data Valid
	Maximum time the memory device has to output valid data after the device outputs a valid
	address.
TCHDV	CLKOUT High to Input Data Valid
	Maximum time the memory system has to output valid data after CLKOUT rises.
TCLDV	CLKOUT Low to Input Data Valid
	Maximum time the memory system has to output valid data after CLKOUT falls.
TQVWH	Data Valid to WR# High
	Time between data being valid on the bus and WR# going inactive.
TRHDZ	RD# High to Input Data Float
	Time after RD# is inactive until the memory system must float the bus. If this timing is not met,
	bus contention will occur.
TRLDV	RD# Low to Input Data Valid
	Maximum time the memory system has to output valid data after the device asserts RD#.
TSLDV	CSx# Valid to Input Data Valid
	Maximum time the memory device has to output valid data after the device outputs a valid chip-
	select output.

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