Intel Microcontroller, 80C196NU, 8XC196NP manual Determining the Source of an Interrupt

STANDARD AND PTS INTERRUPTS

6.At the end of the service routine, the POPA instruction restores the original contents of the PSW, INT_MASK, INT_MASK1, and WSR registers; any changes made to these registers during the interrupt service routine are overwritten. Because interrupt calls cannot occur immediately following a POPA instruction, the last instruction (RET) will execute before another interrupt call can occur.

Notice that the “preamble” and exit code for this routine does not save or restore register RAM. The interrupt service routine is assumed to allocate its own private set of registers from the lower register file. The general-purpose register RAM in the lower register file makes this quite practi- cal. In addition, the RAM in the upper register file is available via windowing (see “Windowing” on page 5-13).

6.5.3Determining the Source of an Interrupt

When the transition detector detects an interrupt, it sets the corresponding bit in the INT_PEND or INT_PEND1 register (Figures 6-7 and 6-8). This bit is set even if the individual interrupt is disabled (masked). The pending bit is cleared when the program vectors to the interrupt service routine. INT_PEND and INT_PEND1 can be read, to determine which interrupts are pending. They can also be modified (written), either to clear pending interrupts or to generate interrupts under software control. However, we recommend the use of the read-modify-write instructions, such as AND and OR, to modify these registers.

ANDB	INT_PEND,	#11111110B	;	Clears the OVRTM1 pending bit
ORB	INT_PEND,	#00000001B	;	Sets the OVRTM1 pending bit

Other methods could result in a partial interrupt cycle. For example, an interrupt could occur dur- ing an instruction sequence that loads the contents of the interrupt pending register into a tempo- rary register, modifies the contents of the temporary register, and then writes the contents of the temporary register back into the interrupt pending register. If the interrupt occurs during one of the last four states of the second instruction, it will not be acknowledged until after the completion of the third instruction. Because the third instruction overwrites the contents of the interrupt pend- ing register, the jump to the interrupt vector will not occur.

An overrun on the EPA capture compare channels can generate the multiplexed capture overrun interrupts (OVR0_1 and OVR2_3). Read the EPA_PEND register to determine the source of the interrupt request (Figure 10-12 on page 10-23).

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