Intel 8XC196NP, 80C196NU, Microcontroller manual Testing the Printed Circuit Board

ARCHITECTURAL OVERVIEW

2.6.2Testing the Printed Circuit Board

The on-circuit emulation (ONCE) mode electrically isolates the 8XC196 device from the system. By invoking ONCE mode, you can test the printed circuit board while the device is soldered onto the board.

2.7DESIGN CONSIDERATIONS FOR 80C196NP TO 80C196NU CONVERSIONS

This section summarizes differences to consider when converting your design requirements from the 80C196NP to the 80C196NU.

•The 80C196NU can achieve an operating frequency of 50 MHz, while the 80C196NP can achieve only 25 MHz.

•The 80C196NU is pin-compatible with the 80C196NP. The functions of four pins differ:

— the 80C196NU has PLLEN1 in place of a no-connection pin of the 80C196NP

— the 80C196NU has PLLEN2 in place of a V SS pin of the 80C196NP

— the 80C196NU has a V CC pin in place of a no-connection pin of the 80C196NP

— the 80C196NU has a no-connection pin in place of the EA# pin of the 80C196NP

•The 80C196NU requires that you tie the PLLEN1 and PLLEN2 pins either high or low, depending on the clock multiplier mode you select.

•The 80C196NU requires that you connect an external capacitor to the RPD pin if your design uses both powerdown mode and a clock multiplier mode.

•The 80C196NU has a new, 32-bit accumulator register and an accumulator status register to support its multiply-accumulate functions.

•The 80C196NU, since it has no nonvolatile memory, has no REMAP bit in the CCB.

•The 80C196NU can window additional memory into the lower register file via a second window selection register (WSR1).

•Unlike the 80C196NP, the 80C196NU’s EPORT special-function registers are located in SFR address space, rather than in memory-mapped space, so they can be windowed for direct access.

•The 80C196NU has an 8-byte prefetch queue, while the 80C196NP has a 4-byte prefetch queue.

•In the 80C196NU, data accesses have a higher priority than instruction queue fetches. In the 80C196NP, the opposite is true (instruction fetches have the highest priority).

•The 80C196NU’s serial I/O port has a divide-by-2 prescaler, controlled by the SP_CON register.

•The 80C196NU’s EPA has an a dditional prescaler option (divide-by-128), controlled by the timer control register (Tx_CONTROL).

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