Intel 8XC196NP, 80C196NU manual Table A-8. Instruction Lengths and Hexadecimal Opcodes, Subc Subcb

INSTRUCTION SET REFERENCE

Table A-8. Instruction Lengths and Hexadecimal Opcodes

Arithmetic (Group I)

	Direct		Immediate		Indirect			Indexed
					(Note 1)			(Notes 1, 2)
Mnemonic
	Length	Opcode	Length	Opcode	Length	Opcode		Length		Opcode
								S/L
ADD (2 ops)	3	64	4	65	3	66		4/5		67
ADD (3 ops)	4	44	5	45	4	46		5/6		47
ADDB (2 ops)	3	74	3	75	3	76		4/5		77
ADDB (3 ops)	4	54	4	55	4	56		5/6		57
ADDC	3	A4	4	A5	3	A6		4/5		A7
ADDCB	3	B4	3	B5	3	B6		4/5		B7
CLR	2	01	—	—	—	—	—		—
CLRB	2	11	—	—	—	—	—		—
CMP	3	88	4	89	3	8A		4/5		8B
CMPB	3	98	3	99	3	9A		4/5		9B
CMPL	3	C5	—	—	—	—	—		—
DEC	2	05	—	—	—	—	—		—
DECB	2	15	—	—	—	—	—		—
EXT	2	06	—	—	—	—	—		—
EXTB	2	16	—	—	—	—	—		—
INC	2	07	—	—	—	—	—		—
INCB	2	17	—	—	—	—	—		—
SUB (2 ops)	3	68	4	69	3	6A		4/5		6B
SUB (3 ops)	4	48	5	49	4	4A		5/6		4B
SUBB (2 ops)	3	78	3	79	3	7A		4/5		7B
SUBB (3 ops)	4	58	4	59	4	5A		5/6		5B
SUBC	3	A8	4	A9	3	AA		4/5		AB
SUBCB	3	B8	3	B9	3	BA		4/5		BB

NOTES:

1.Indirect normal and indirect autoincrement share the same opcodes, as do short- and long-indexed modes. Because word registers always have even addresses, the address can be expressed in the upper seven bits; the least-significant bit determines the addressing mode. Indirect normal and short- indexed modes make the second byte of the instruction even (LSB = 0). Indirect autoincrement and long-indexed modes make the second byte odd (LSB = 1).

2.For indexed instructions, the first column lists instruction lengths as S/L, where S is the short-indexed instruction length and L is the long-indexed instruction length.

3.For the SCALL and SJMP instructions, the three least-significant bits of the opcode are concatenated with the eight bits to form an 11-bit, 2’s complement offset.

A-53