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Intel 80C196NU, 8XC196NP, Microcontroller Quadrature Mode Interface Quadrature Mode Truth Table

Models: Microcontroller 80C196NU 8XC196NP

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EVENT PROCESSOR ARRAY (EPA)

	Increment	8XC196 Device
		8XC196 Device
	Decrement
				PH2
	X			PH1
				PH1
	Y
	TxCLK
	D Q	D Q	D Q	X_internal
Optical
Reader	TxDIR
	TxDIR
	D Q	D Q	D Q	Y_internal
				A0268-02

Figure 10-3. Quadrature Mode Interface

Table 10-3. Quadrature Mode Truth Table

	State of X_internal	State of Y_internal	Count Direction
	(TxCLK)	(TxDIR)	Count Direction
	(TxCLK)	(TxDIR)

	−	0	Increment
	↓	1	Increment
	0	↓	Increment
	1	−	Increment
	↓	0	Decrement
	−	1	Decrement
	0	−	Decrement
	1	↓	Decrement

10-7

Image 204

Intel 80C196NU, 8XC196NP, Microcontroller manual Quadrature Mode Interface Quadrature Mode Truth Table

Contents

8XC196NP, 80C196NU Microcontroller User’ Manual 8XC196NP, 80C196NU Microcontroller User’s Manual Intel Corporation Contents Chapter Programming Considerations Contents Chapter Ports Programming the Serial Port EPA Functional Overview8XC196NP, 80C196NU USER’S Manual Chapter Interfacing with External Memory Appendix C Registers Glossary Index Figures 10-7 Valid EPA Input Events 13-16 Tables 10-5 Example Control Register Settings and EPA Operations 8XC196NP and 80C196NU Signals Arranged by Function Guide to This Manual Page Manual Contents Chapter Guide to this Manual8XC196NP, 80C196NU USER’S Manual Notational Conventions and Terminology AddressesItalics Units of measure Related DocumentsHandbooks and Product Information Application Notes, Application Briefs, and Article ReprintsTitle Order Number MCS 96 Microcontroller Datasheets Commercial/Express MCS 96 Microcontroller Datasheets Automotive8XC196NP, 80C196NU USER’S Manual Intentionally Left Blank Intentionally Left Blank World Wide Web Technical SupportProduct Literature Page Architectural Overview Page Chapter Architectural Overview Typical ApplicationsDevice Features Block DiagramFeatures of the 8XC196NP and 80C196NU ROMCPU Control Register FileRegister Arithmetic-logic Unit Ralu Code ExecutionMemory Controller Instruction FormatInterrupt Service Multiply-accumulate 80C196NU OnlyInternal Timing Clock Circuitry 8XC196NPClock Circuitry 80C196NU State Times at Various Frequencies 12.5 MHz25 MHz 50 MHzPLLEN21 Multiplier State TimeEvent Processor Array EPA and Timer/Counters Internal Peripherals1 I/O Ports Serial I/O SIO PortReducing Power Consumption Pulse-width Modulator PWMSpecial Operating Modes Testing the Printed Circuit Board Design Considerations for 80C196NP to 80C196NU Conversions8XC196NP, 80C196NU USER’S Manual Advanced Math Features Page Chapter Advanced Math Features Enhanced Multiplication InstructionsSaturation Mode Operating ModesMultiply/Accumulate Example Code Instructions Execution TimeFractional Mode Accumulator Register ACC0x Accumulator Control and Status Register Accstat AccstatBit Function Number Mnemonic Effect of SME and FME Bit Combinations SME FMEDescription Programming Considerations Page Overview of the Instruction SET Operand Type DefinitionsOperand Type No. Signed Possible Values Addressing RestrictionsBIT Operands Byte OperandsSHORT-INTEGER Operands Word Operands Integer OperandsDOUBLE-WORD Operands LONG-INTEGER Operands QUAD-WORD OperandsConverting Operands Conditional JumpsFloating Point Operations Extended InstructionsEST Addressing ModesDirect Addressing Immediate AddressingIndirect Addressing Definition of Temporary RegistersExtended Indirect Addressing Indirect Addressing with AutoincrementExtended Indirect Addressing with Autoincrement Indexed Addressing Indirect Addressing with the Stack PointerShort-indexed Addressing Long-indexed AddressingExtended Indexed Addressing Zero-indexed AddressingExtended Zero-indexed Addressing Assembly Language Addressing Mode Selections Extended AddressingDesign Considerations for 1-MBYTE Devices Software Standards and ConventionsUsing Registers Addressing 32-bit OperandsAddressing 64-bit Operands Linking Subroutines Software Protection Features and Guidelines Memory Partitions Page Chapter Memory Partitions Memory MAP OverviewFFH 2FH 1FH 0FH F1H F0HMemory Partitions FFH80C196NP/NU External 83C196NP ROM XC196NP and 80C196NU Memory Map Hex Description Addressing ModesProgram Memory Access for the 83C196NP External MemoryProgram and Special-purpose Memory Program Memory in Page FFHSpecial-purpose Memory Access for the 83C196NP Special-purpose MemoryXC196NP and 80C196NU Special-purpose Memory Addresses Chip Configuration Bytes Peripheral Special-function Registers SFRsReserved Memory Locations Interrupt and PTS VectorsPeripheral SFRs 1F7EH 1F7CH1F7AH 1F4EHStack Pointer CPU SFRsRegister File Memory Addresses General-purpose Register RAMStack Pointer SP Address Description Addressing Modes RangeCPU Special-function Registers SFRs CPU SFRs8XC196NP CPU SFRs Address High Odd Byte Low Even Byte 80C196NU CPU SFRs Address High Odd Byte Low Even ByteWindowing 8XC196NPSelecting a Window WSRHlden Bit FunctionSelecting a Window of the Upper Register File Addressing a Location Through a Window 10. Windows Base WSR or WSR1 Value WSR Value forPeripheral SFRs Upper Register File11. Windowed Base Addresses 2.1 32-byte Windowing Example2.2 64-byte Windowing Example 2.3 128-byte Windowing ExampleUsing the Linker Locator to Set Up a Window Unsupported Locations Windowing Example 8XC196NP OnlyType Base Length Alignment This listing shows the disassembled code Windowing and Addressing ModesRemapping Internal ROM 83C196NP only Accessing Data Fetching Code and Data in the 1-MBYTE and 64-KBYTE ModesFetching Instructions EpcpcFormation of Extended and Nonextended Addresses Code Fetches in the 1-Mbyte Mode Code Fetches in the 64-Kbyte ModeData Fetches in the 1-Mbyte and 64-Kbyte Modes 80C196NP and 80C196NUMemory Configuration Examples Example 1 Using the 64-Kbyte ModeRD# WR# CE#12. Memory Map for the System in Figure Address Description80C196NP and 80C196NU External flash memory 80C196NP and 80C196NU UnimplementedExample 2 a 64-Kbyte System with Additional Data Storage RD# WR# CE#Ffffffh D70 OE# WE# 02FFFFH13. Memory Map for the System in Figure 80C196NP and 80C196NU External RAMExample 3 Using 1-Mbyte Mode 01FFFFHOE# WE# OE# WRH# WRL# RD# 14. Memory Map for the System in Figure 80C196NP and 80C196NU External memoryFbffffh Standard and PTS Interrupts Page Chapter Standard and PTS Interrupts Overview of InterruptsFlow Diagram for PTS and Standard Interrupts Interrupt Signals and Registers Interrupt SignalsInterrupt and PTS Control and Status Registers Interrupt Sources and Priorities Special InterruptsIntpend PtsselInterrupt Controller PTS Service Interrupt Sources, Vectors, and PrioritiesUnimplemented Opcode Software TrapExternal Interrupt Pins Multiplexed Interrupt SourcesEnd-of-PTS Interrupts 1.3 NMIInterrupt Latency Situations that Increase Interrupt LatencyCalculating Latency Standard Interrupt LatencyStandard Interrupt Response Time PTS Interrupt Latency PTS Mode Execution Time in State Times Programming the InterruptsExecution Times for PTS Cycles Programming Considerations for Multiplexed Interrupts PtsselBit Mnemonic Interrupt PTS Vector Intmask EPA0 EXTINT1 EXTINT0 OVRTM2 OVRTM1Bit Mnemonic Interrupt Standard Vector Modifying Interrupt Priorities INTMASK1NMI EXTINT3 EXTINT2 EPA3 EPA2 EPA1RET Cseg AT 0FF200CH Determining the Source of an Interrupt Interrupt Pending Intpend Register IntpendInitializing the PTS Control Blocks INTPEND1PWM Toggle Mode PWM Remap ModeSpecifying the PTS Count Single TransferSelecting the PTS Mode PtssrvEPA3 EPA2 EPA1 EXTINT0 OVRTM1 OVRTM2 Single Transfer Mode PtsconAddress Ptspcb + PTS Single Transfer Mode Control Block Ptsdst HI Ptsdst LO Ptssrc HI Ptssrc LO Ptscon PtscountRegister Location Function Ptsdst Ptscb +8XC196NP, 80C196NU USER’S Manual Block Transfer Mode Single Transfer Mode PtscbBlock Transfer Mode Ptscb Ptscount = 09HPTS Block Transfer Mode Control Block Ptsblock Ptscb +Increment the contents of Ptssrc after each byte or word PWM Toggle Mode PWM Remap Mode PWM ModesComparison of PWM Modes PTSCONST2PWM Toggle Mode Example 14. a Generic PWM WaveformPWM Toggle Mode Ptscb PTSCONST1 HI = T1 HI PTSCONST1 LO = T1 LO PTSPTR1 HI = 1FHPTSCONST2 H PTSCONST2 LPTSCONST1 H PTSCONST1 LPtscon Ptscb + Tmod16. EPA and PTS Operations for the PWM Toggle Mode Example PWM Remap Mode Example PWM Remap Mode Ptscb PTS PWM Remap Mode Control Block PTSCONST1 HI PTSCONST1 LO PTSPTR1 HI PTSPTR1 LO PtsconPTS PWM Remap Mode Control Block Register PWM Tmod18. EPA and PTS Operations for the PWM Remap Mode Example Ports Page I/O Ports Overview Bidirectional PortsDevice I/O Ports Port Bits TypeBidirectional Port Pins Port Pin Special-function Associated SignalsBidirectional Port Operation Bidirectional Port Control and Status Registers8XC196NP, 80C196NU USER’S Manual Bidirectional Port Structure Logic Table for Bidirectional Ports in I/O Mode SfdirBidirectional Port Pin Configurations Bidirectional Port Pin Configuration Example Control Register Values for Each ConfigurationPort Configuration Example Bidirectional Port Considerations HZ1P2.7/CLKOUT Eport Pins Port Pin Extended-address Signal TypeDesign Considerations for External Interrupt Inputs EportEport Operation 10. Eport Control and Status RegistersEport Block Diagram Reset Output EnableComplementary Output Mode Open-drain Output ModeEport Structure Input Mode 11. Logic Table for Eport in I/O Mode12. Logic Table for Eport in Address Mode Epmode Epdir EpregConfiguring Eport Pins Configuring Eport Pins for Extended-address FunctionsConfiguring Eport Pins for I/O 13. Configuration Register Settings for Eport PinsEport Considerations Eport Status During Instruction ExecutionDesign Considerations Page Serial I/O SIO Port Page SIO Block Diagram Serial I/O SIO Port Functional OverviewSerial I/O Port Signals and Registers Serial Port SignalsSerial Port Control and Status Registers SerialP1REG 1FD4H Sbufrx 1FB8HSbuftx 1FBAH Spbaud 1FBCH,1FBDHSynchronous Mode Mode Serial Port ModesSpstatus 1FB9H Mode 0 Timing Asynchronous Modes Modes 1, 2,Serial Port Frames for Mode ModeSerial Port Frames in Mode 2 Mode 2 and 3 TimingsConfiguring the Serial Port Pins Programming the Serial PortProgramming the Control Register Programming the Baud Rate and Clock SourceSpcon PAR TB8 PRS REN PENPAR Spcon Bit FunctionSpbaud Spbaud Values When Using the Internal Clock at 25 MHz Baud Rate Spbaud Register Value Note Error Mode Mode 1, 28A2BH Baud Rate Spbaud Register Value † Error Mode Enabling the Serial Port InterruptsDetermining Serial Port Status 8A2CHSpstatus RPE/RB8 TXERPE/RB8 Serial I/O SIO Port Page Pulse-width Modulator Page PWM Block Diagram 8XC196NP Only PWM Functional OverviewPWM Signals and Registers PWM SignalsPWM Operation PWM Control and Status Registers8XC196NP, 80C196NU USER’S Manual Enabled Programming the Frequency and PeriodE6H FFHPWM Output Frequencies 8XC196NP PWM Output Frequencies 80C196NUCLK0 CLK1 CLK0Programming the Duty Cycle CONREG0FEH CLK1 CLK0Disabled Clock PrescalerPWM xCONTROL Address PWM Duty CyclePWM Output Alternate Port Function PWM Output Enabled When Sample CalculationsEnabling the PWM Outputs PWM Output Alternate FunctionsD/A Buffer Block Diagram Event Processor Array EPA Page Chapter Event Processor Array EPA EPA Functional OverviewEPA and TIMER/COUNTER Signals and Registers EPA and Timer/Counter SignalsPort Pin EPA Signals EPAEPA Control and Status Registers TIMER1 TIMER2TIMER/COUNTER Functional Overview EPA Timer/CountersCascade Mode Timer 2 Only Quadrature Clocking ModeQuadrature Mode Interface Quadrature Mode Truth Table Quadrature Mode Timing and Count EPA Channel Functional OverviewOperating in Capture Mode A Single EPA Capture/Compare ChannelEPA Simplified Input-capture Structure Action Taken when a Valid Edge Occurs Action taken when a valid edge occursEPA Overruns EPAxCON.0Operating in Compare Mode Preventing EPA OverrunsGenerating a Low-speed PWM Output Generating a Medium-speed PWM Output Generating a High-speed PWM Output Programming the EPA and TIMER/COUNTERS Configuring the EPA and Timer/Counter Port PinsProgramming the Timers Generating the Highest-speed PWM OutputPrescaler Divisor Resolution † T1CONTROLClock Source Direction Source Prescaler Resolution † T2CONTROLExample Control Register Settings and EPA Operations Mode ROT ON/RTProgramming the Capture/Compare Channels EPA xCON Address Reset State 00H = 1 = 0ROT ON/RT Capture Mode Event Compare Mode ActionCapture Mode on Compare Mode RTROT Enabling the EPA Interrupts Determining Event StatusEpamask 12. EPA Interrupt Pending Epapend Register Epapend †Programming Examples for EPA Channels EPA Capture Event Program EPA PWM Output Program Unsigned char Unused Ptscon10-27 Page Minimum Hardware Considerations Page Minimum Required Signals SignalMinimum Connections I/O Port Configuration Guide Port Where to Find Configuration InformationUnused Inputs 11.1.2 I/O Port Pin ConnectionsMinimum Hardware Connections Applying and Removing Power Noise Protection TipsON-CHIP Oscillator Circuitry On-chip Oscillator CircuitExternal Crystal Connections Using AN External Clock Source External Clock ConnectionsResetting the Device Reset Timing SequenceGenerating an External Reset Internal Reset CircuitryMinimum Reset Circuit Issuing the Reset RST Instruction Issuing an Illegal Idlpd Key OperandPage Special Operating Modes Page Special Operating Mode Signals and Registers Operating Mode Control SignalsPort Pin Signal Type Description Name OnceOperating Mode Control and Status Registers Port Pin Signal Type DescriptionPLLEN21 CCR0Reducing Power Consumption P2DIR 1FD3HP2MODE 1FD1H P2REG 1FD5HClock Control During Power-saving Modes 8XC196NP Idle Mode Clock Control During Power-saving Modes 80C196NUStandby Mode 80C196NU only Enabling and Disabling Standby ModeEntering Standby Mode Exiting Standby Mode Powerdown ModeEnabling and Disabling Powerdown Mode Entering Powerdown ModeExiting Powerdown Mode Generating a Hardware ResetAsserting an External Interrupt Signal External RC Circuit Selecting C1 Typical Voltage on the RPD Pin While Exiting Powerdown Once Mode Reserved Test Modes 80C196NU onlyC196NU Clock Modes PLLEN2 PLLEN1Page Interfacing with External Memory Page Internal and External Addresses Example of Internal and External AddressesExternal Memory Interface Signals External Memory Interface SignalsBit Multiplexed Bus Mode Bit Demultiplexed ModeBytes Accessed Description Multiplexed WithALE BHE#Name Type Description Multiplexed With EA#Inst ReadyCHIP-SELECT Unit WRL#WRH# Chip-select Registers Register Address Description MnemonicAddrcom Address Reset State Defining Chip-select Address RangesRegister Address Addrmsk Address Reset State Register Address Reset ValueBase Addresses for Several Sizes of the Address Range Address Mbyte Kbyte BytesFFB00H FFE00H FFD00H FFF00H Buscon Address Reset State Controlling Wait States, Bus Width, and Bus MultiplexingWS1 WS0 Wait StatesBUSCONx Addresses and Reset Values Chip-select Unit Initial ConditionsInitializing the Chip-select Registers Example of a Chip-select Setup Chip Contents SramUart BusconChip Configuration Registers and Chip Configuration Bytes Chip Address Size Number ContentsResults for the Chip-select Example Addrcom AddrmskCCR0 WS1 WS0 Demux BHE#WS0 WS1 CCR1 Remap MODE64Remap 13-17 BUS Width and Multiplexing Bit Demultiplexed Bus Bit Multiplexed BusBit Demultiplexed Bus ALE ALEBit Multiplexed Bus 13.5.1 a 16-bit Example System 13.5.2 16-bit Bus Timings CS#Clkout ALE RD#13.5.3 8-bit Bus Timings A190 Address AD158 High Address Comparison of Multiplexed and Demultiplexed Buses Wait States Ready ControlBus Description Demultiplexed Bus ns† Multiplexed Bus ns† 11. Ready Signal Timing Definitions Symbol DefinitionReady ALE BHE#, Inst14. Ready Timing Diagram Demultiplexed Mode 8XC196NP 15. Ready Timing Diagram Demultiplexed Mode 80C196NU BUS-HOLD ProtocolSymbol Parameter 12. HOLD#, HLDA# Timing DefinitionsEnabling the Bus-hold Protocol Disabling the Bus-hold ProtocolHold Latency Regaining Bus Control WRITE-CONTROL Modes13. Maximum Hold Latency Bus Cycle Type14. Write Signals for Standard and Write Strobe Modes ALE WR# WRL#BHE# WRH# Bus Word/Byte Standard Write Strobe18. Decoding WRL# and WRH# System BUS AC Timing Specifications RD# WRH# WRL#WE# OE# 20. Multiplexed System Bus Timing 8XC196NP 21. Multiplexed System Bus Timing 80C196NU 22. Demultiplexed System Bus Timing 8XC196NP Deferred Bus-cycle Mode 80C196NU Only 23. Demultiplexed System Bus Timing 80C196NU24. Deferred Bus-cycle Mode Timing Diagram 80C196NU Explanation of AC Symbols 15. AC Timing Symbol Definitions SignalsAC Timing Definitions ConditionsSymbol Definition 8XC196Nx Meets These Specifications 13-44 13-45 Page Instruction Set Reference Page Appendix a Instruction SET Reference Table A-1. Opcode Map Left Half OpcodeTable A-1. Opcode Map Right Half Table A-2. Processor Status Word PSW Flags Mnemonic DescriptionValue of Bits Shifted Off Instruction Quotient Stored Flag Set if Quotient isTable A-4. PSW Flag Setting Symbols Symbol DescriptionInstruction Jumps to Destination if Continues if Table A-5. Operand Variables Variable DescriptionPSW Flag Settings Table A-6. Instruction SetMnemonic Operation C V VT STInstruction Format Dest ← Dest and SRCAndb Bmov PTRS, CntregMnemonic Operation Instruction Format Count ← CountDest PC ← DestClear WORD. Clears the value Compare BYTES. Subtracts the source DIV Dest MOD SRC← Dest MOD SRC Djnz Decrement and Jump if not ZeroDpts Disable Peripheral Transaction Djnzw Decrement and Jump if not ZeroEbmovi Extended Interruptable Block PTRS, Cntreg Count ← CntregDstptr ← Ptrs + Dstptr ← Srcptr Ptrs ← Srcptr + EBROnto the stack, then adds to the program Epts Enable Peripheral Transaction ELDSRC, Dest EXT SIGN-EXTEND Integer Into LongExtb SIGN-EXTEND SHORT-INTEGER Into ExtbIncrement WORD. Increments the value Word operand by Mnemonic Operation Instruction Format JGE Jump if Signed Greater than orJGT JLE Jump if Signed Less than or EqualNegative flag is set, this instruction adds JNH JNV Jump if Overflow Flag is ClearJnvt Jump if OVERFLOW-TRAP Flag is JnvtJVT Jump if OVERFLOW-TRAP Flag is SET JVTKbyte mode Mbyte modeMUL MulbMulu MuluDest ← Dest PSW Flag Settings MulubNEG Negate INTEGER. Negates the valueMnemonic Dest ← not DestDest ← Dest or SRC ORBINTMASK1/WSR ← SP PSW/INTMASK ← SPSP ← PSW/INTMASK PSW/INTMASK ← SP ← INTMASK1/WSR INTMASK1 ←RST ScallWreg,#count Shll SHRRange of 0 to 31 1FH, inclusive. If Shral Arithmetic Right Shift Double ShralShrl Logical Right Shift DOUBLE-WORD SkipRightmost operand SUBSubb Subc Subtract Words with Borrow DEST, SRCSubc Subcb Subtract Bytes with Borrow DEST, SRCTijmp TBASE, INDEX, #MASK Index and #MASK = Offset × Offset + Tbase = Dest PC ← DestMnemonic SRCXOR Dest ← Dest XOR SRCTable A-7. Instruction Opcodes Hex Code Instruction MnemonicClrb Notb Negb Decb Extb Incb Shrb Shlb ShrabHex Code Instruction SET Reference 8XC196NP, 80C196NU USER’S Manual ST Direct ELD Indirect Table A-8. Instruction Lengths and Hexadecimal Opcodes Arithmetic Group Direct Immediate Indirect Indexed MnemonicSubc Subcb Logical Direct Immediate Indirect Stack Direct Immediate Indirect Indexed Mnemonic Opcode LengthPOP Popa Popf Push Pusha Pushf Data Direct Immediate ExtendedEbmovi ELD Eldb EST Estb Direct ImmediateJump Direct Immediate EBR EjmpCall Direct Immediate Lcall RETDjnz Djnzw JBC JGE JGT JLE JLT JNC JNE JNH Jnst JNV Jnvt JST JVTShift Mnemonic Direct Immediate Indirect Indexed Length OpcodeSpecial Mnemonic Direct Immediate Indirect PTSTable A-9. Instruction Execution Times in State Times Arithmetic Group IndirectNormal Autoinc Short Long Reg Mem Mem RegMnemonic Direct Immed Normal Autoinc Short Long Reg Mem DIV Divb Divu DivubLogical Stack Register Indirect Normal Autoinc ShortReg Mem Data Mnemonic Extended-indirect Normal Extended-indexedIndexed Mnemonic Autoinc Short Long Reg MemMnemonic Direct Immed Ljmp Sjmp TijmpIndirect Indexed Mnemonic Direct Immed Autoinc Short LongConditional Jump Mnemonic Short-IndexedShift Mnemonic DirectSpecial Mnemonic Direct Immed Indirect Indexed Clrc Clrvt IdlpdNOP RST Setc Skip Immed Indirect IndexedPage Signal Descriptions Page Functional Groupings of Signals Table B-1 XC196NP and 80C196NU Signals Arranged by FunctionFigure B-1 XC196NP 100-lead Sqfp Package X8XC196NPFigure B-2 XC196NP 100-lead QFP Package Figure B-3 C196NU 100-lead Sqfp Package X8XC196NUFigure B-4 C196NU 100-lead QFP Package Signal Descriptions Table B-3. Signal DescriptionsTable B-2. Description of Columns of Table B-3 Column Heading Description NameByte High Enable† WRH# BREQ#EPORT.30 EXTINT30HOLD# VSSName Type Description PLLEN1 PLLEN2VSS if either of the following conditions are true Asserted only during external memory writes Default Conditions Table B-4. Definition of Status SymbolsRESET# NP/NU RESET#Ready WK1 RESET# RPD WK1 EPORT.30ALE WK0 BHE# WK1Registers Page Chip Configuration Table C-1. Modules and Related RegistersCPU EPA InterruptsTable C-2. Register Name, Address, and Reset Status EPA3CON EPA2TIMEEPA3TIME 1FD6H Xxxx P1REGXxxx Spbaud WSR1 NUTable C-3. ACC0x Addresses and Reset Values ACC0xACC0x Accstat AccstatTable C-4. Effect of SME and FME Bit Combinations SME FMETable C-5. ADDRCOMx Addresses and Reset Values ADDRCOMxAddrcom Address Table C-6. ADDRMSKx Addresses and Reset Values ADDRMSKx Address Table C-6 Reset StateADDRMSKx Table C-7. BUSCONx Addresses and Reset Values BUSCONxBuscon Address CCR0 CCR0CCR1 CCR1CONREG0 CONREG0Epdir PIN3 PIN2 PIN1 PIN0Epmode EpmodeEppin XXHEpreg X0HEpamask EpamaskEpapend EpapendEPAxCON EPA xCON AddressEPAxCON Address Table C-8 Bit FunctionBit Function Number Table C-8. EPAxCON Addresses and Reset Values Register Address Reset ValueTable C-9. EPAxTIME Addresses and Reset Values EPAxTIMEIntmask IntmaskINTMASK1 FF203EH EXTINT3FF203CH EXTINT2 Intpend IntpendINTPEND1 INTPEND1Onesreg OnesregFfffh 150 One These bits are always equal to FfffhTable C-10. PxDIR Addresses and Reset Values PxDIRXDIR Address PIN7 PIN6 PIN5 PIN4 PIN3 PIN2 PIN1 PIN0Table C-11. PxMODE Addresses and Reset Values Table C-12. Special-function Signals for PortsPxMODE Table C-13. PxPIN Addresses and Reset Values PxPINXPIN Address Bit NumberTable C-14. PxREG Addresses and Reset Values PxREGPxREG Address Table C-14 P1REG 1FD4H FFH P2REG 1FD5H P3REG 1FDCH P4REG 1FDDHPSW PSWPSE PSW Bit Function Number MnemonicPtssel PtsselPtssrv FF200AH EXTINT1Table C-15. PWMxCONTROL Addresses and Reset Values PWMxCONTROLSbufrx SbufrxData Received Sbuftx SbuftxData to Transmit Xxxxh Spbaud SpbaudBaud Rate Spbaud Register Value Note Error Mode Mode 1, 2Spcon SpconSpstatus T1CONTROL T1CONTROLT2CONTROL T2CONTROLTIMERx Table C-17. TIMERx Addresses and Reset ValuesTimer Address WSR Byte WindowsRegister Memory 00E0-00FFH Mnemonic LocationRegister Memory 00E0-00FFH 00C0-00FFH TIMER1 † TIMER2 †P4DIR 1FDBH 7EH 00FBH 3FH 00DBH 1FH P4MODE 1FD9H PWM1CONTROL 1FB2H 7DHWSR1 Register Memory 0060-007FH 0040-007FH Mnemonic Location0060-007FH 0040-007FH Mnemonic Location PWM0CONTROL 1FB0H 7DH Sbuftx 1FBAH 7DHSpbaud 1FBCH 7DH Spcon 1FBBH 7DHZeroreg Zeroreg150 Zero This register is always equal to zero Page Glossary Page Glossary DOUBLE-WORD FET ISR PIC PLL PTS SFR Uart Index Page Index Index-2 Index-3 Index-4 Index-5 Index-6 Index-7 Index-8 Index-9 Index-10 Index-11 Index-12