Intel 80C196NU Defining Chip-select Address Ranges, Addrcom Address Reset State, Register Address

INTERFACING WITH EXTERNAL MEMORY

13.3.1 Defining Chip-select Address Ranges

This section describes the ADDRCOMx and ADDRMSKx registers and how to set them up for

adesired address range. The ADDRCOMx register (Figure 13-2) and ADDRMSKx register (Fig- ure 13-3) control the assertion of each chip-select output CSx#. The BASE19:8 bits in the ADDRCOMx register determine the base address of the address range. The MASK19:8 bits in the ADDRMSKx register determine the size of the address range.

ADDRCOMx	Address:	Table 13-4
x = 0–5	Reset State:

The address compare (ADDRCOMx) register specifies the base (lowest) address of the address range. The base address of a 2n-byte address range must be on a 2n-byte boundary.

15

— — — —

7

BASE15 BASE14 BASE13 BASE12

8

BASE19 BASE18 BASE17 BASE16

0

BASE11 BASE10 BASE9 BASE8

Bit	Bit	Function
Number	Mnemonic
15:12	—	Reserved; for compatibility with future devices, write zeros to these bits.
11:0	BASE19:8	Base Address Bits
		These bits are the 12 most-significant bits of the base address of the
		address range assigned to chip-select x.

Figure 13-2. Address Compare (ADDRCOMx) Register

Table 13-4. ADDRCOMx Addresses and Reset Values

Register Address Reset Value

ADDRCOM01F40H0F20H

ADDRCOM11F48HX000H

ADDRCOM21F50HX000H

ADDRCOM31F58HX000H

ADDRCOM41F60HX000H

ADDRCOM51F68HX000H

13-7