Intel 8XC196NP, 80C196NU, Microcontroller manual Table A-1. Opcode Map Left Half

8XC196NP, 80C196NU USER’S MANUAL

Table A-1. Opcode Map (Left Half)

Opcode	x0	x1	x2		x3	x4	x5		x6		x7
0x	SKIP	CLR	NOT		NEG	XCH	DEC		EXT		INC
						di
1x		CLRB	NOTB		NEGB	XCHB	DECB		EXTB		INCB
						di
2x					SJMP
3x					JBC
	bit 0	bit 1	bit 2		bit 3	bit 4	bit 5		bit 6		bit 7
4x		AND 3op					ADD 3op
	di	im	in		ix	di	im		in		ix
5x		ANDB 3op					ADDB 3op
	di	im	in		ix	di	im		in		ix
6x		AND 2op					ADD 2op
	di	im	in		ix	di	im		in		ix
7x		ANDB 2op					ADDB 2op
	di	im	in		ix	di	im		in		ix
8x		OR						XOR
	di	im	in		ix	di	im		in		ix
9x		ORB					XORB
	di	im	in		ix	di	im		in		ix
Ax		LD					ADDC
	di	im	in		ix	di	im		in		ix
Bx		LDB					ADDCB
	di	im	in		ix	di	im		in		ix
Cx	ST	BMOV		ST		STB	CMPL			STB
	di		in		ix	di			in		ix
Dx	JNST	JNH	JGT		JNC	JNVT	JNV		JGE		JNE
Ex	DJNZ	DJNZW	TIJMP		BR/EBR	EBMOVI			EJMP		LJMP
					in
Fx	RET	ECALL	PUSHF		POPF	PUSHA	POPA		IDLPD		TRAP

NOTE: The first digit of the opcode is listed vertically, and the second digit is listed horizontally. The related instruction mnemonic is shown at the intersection of the two digits. Shading indicates reserved opcodes. If the CPU attempts to execute an unimplemented opcode, an interrupt occurs. For more information, see “Unimplemented Opcode” on page 6-5.

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