Intel 8XC196NP, 80C196NU, Microcontroller Example Control Register Settings and EPA Operations

	CONTENTS
	TABLES
Table		Page
7-9	EPORT Pins	7-11
7-10	EPORT Control and Status Registers	7-12
7-11	Logic Table for EPORT in I/O Mode	7-16
7-12	Logic Table for EPORT in Address Mode	7-16
7-13	Configuration Register Settings for EPORT Pins	7-17
8-1	Serial Port Signals	8-2
8-2	Serial Port Control and Status Registers	8-2
8-3	SP_BAUD Values When Using the Internal Clock at 25 MHz	8-12
8-4	SP_BAUD Values When Using the Internal Clock at 50 MHz (80C196NU Only)	8-13
9-1	PWM Signals	9-2
9-2	PWM Control and Status Registers	9-3
9-3	PWM Output Frequencies (8XC196NP)	9-6
9-4	PWM Output Frequencies (80C196NU)	9-6
9-5	PWM Output Alternate Functions	9-9
10-1	EPA and Timer/Counter Signals	10-2
10-2	EPA Control and Status Registers	10-3
10-3	Quadrature Mode Truth Table	10-7
10-4	Action Taken when a Valid Edge Occurs	10-11
10-5	Example Control Register Settings and EPA Operations	10-18
11-1	Minimum Required Signals	11-1
11-2	I/O Port Configuration Guide	11-2
12-1	Operating Mode Control Signals	12-1
12-2	Operating Mode Control and Status Registers	12-2
12-3	80C196NU Clock Modes	12-13
13-1	Example of Internal and External Addresses	13-1
13-2	External Memory Interface Signals	13-2
13-3	Chip-select Registers	13-6
13-4	ADDRCOMx Addresses and Reset Values	13-7
13-5	ADDRMSKx Addresses and Reset Values	13-8
13-6	Base Addresses for Several Sizes of the Address Range	13-9
13-7	BUSCONx Addresses and Reset Values	13-11
13-8	BUSCONx Registers for the Example System	13-13
13-9	Results for the Chip-select Example	13-14
13-10	Comparison of AC Timings for Demultiplexed and Multiplexed 16-bit Buses	13-26
13-11	READY Signal Timing Definitions	13-27
13-12	HOLD#, HLDA# Timing Definitions	13-31
13-13	Maximum Hold Latency	13-33
13-14	Write Signals for Standard and Write Strobe Modes	13-34
13-15	AC Timing Symbol Definitions	13-42
13-16	AC Timing Definitions	13-42
A-1	Opcode Map (Left Half)	A-2
A-1	Opcode Map (Right Half)	A-3
A-2	Processor Status Word (PSW) Flags	A-4
A-3	Effect of PSW Flags or Specified Conditions on Conditional Jump Instructions	A-5

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