Intel 8XC196NP, 80C196NU, Microcontroller Extended Indexed Addressing, Zero-indexed Addressing

8XC196NP, 80C196NU USER’S MANUAL

ST	AX,TABLE[BX]	;	MEM_WORD(TABLE+BX) ← AX
ADDB	AL,BL,LOOKUP[CX]	;	AL ← BL + MEM_BYTE(LOOKUP+CX)

The instruction LD AX, TABLE[BX] loads AX with the contents of the memory location that re- sides at address TABLE+BX. That is, the instruction adds the contents of BX (the offset) to the constant TABLE (the base address), then loads AX with the contents of the resulting address. For example, if TABLE equals 4000H and BX contains 12H, then AX is loaded with the contents of location 4012H. Long-indexed addressing is typically used to access elements in a table, where TABLE is a constant that is the base address of the structure and BX is the scaled offset (n × el- ement size, in bytes) into the structure.

4.2.4.3Extended Indexed Addressing

The extended load and store instructions can use extended indexed addressing. The only differ- ence from long-indexed addressing is that both the base address and the offset must be 24 bits to support access to the entire 1-Mbyte address space. The following instructions use extended in- dexed addressing. (In these instructions, OFFSET is a 24-bit variable containing the offset, and EX is a double-word aligned 24-bit register containing the base address.)

ELD	AX,OFFSET[EX]	; AX		← MEM_WORD(EX+OFFSET)
ELDB	AL,OFFSET[EX]	; AL		← MEM_BYTE(EX+OFFSET)
EST	AX,OFFSET[EX]	;	MEM_WORD(EX+OFFSET) ← AX
ESTB AL,OFFSET[EX]		;	MEM_BYTE(EX+OFFSET) ← AL

4.2.4.4Zero-indexed Addressing

In a zero-indexed instruction, you specify the address as a 16-bit variable; the offset is zero, and you can express it in one of three ways: [0], [ZERO_REG], or nothing. Each of the following load instructions loads AX with the contents of the variable THISVAR.

LD AX,THISVAR[0]

LD AX,THISVAR[ZERO_REG]

LD AX,THISVAR

The following instructions also use zero-indexed addressing:

ADD	AX,1234H[ZERO_REG]	;	AX ← AX + MEM_WORD(1234H)
POP	5678H[ZERO_REG]	;	MEM_WORD(5678H) ← MEM_WORD(SP)

;SP ← SP + 2

4.2.4.5Extended Zero-indexed Addressing

The extended instructions can also use zero-indexed addressing. The only difference is that you specify the address as a 24-bit constant or variable. The following extended instruction uses zero- indexed addressing. ZERO_REG acts as a 32-bit fixed source of the constant zero for an extended indexed reference.

ELD AX,23456H[ZERO_REG] ; AX ← MEM_WORD(23456H)

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