Intel 80C196NU, 8XC196NP, Microcontroller manual Exiting Powerdown Mode, Generating a Hardware Reset

8XC196NP, 80C196NU USER’S MANUAL

After completing these tasks, execute the IDLPD #2 instruction to enter powerdown mode.

NOTE

To prevent an accidental return to full power, hold the external interrupt pins (EXTINTx) low while the device is in powerdown mode.

12.5.3 Exiting Powerdown Mode

The device will exit powerdown mode when either of the following events occurs:

•a hardware reset is generated, or

•a transition occurs on an external interrupt pin.

NOTE

It was previously documented that the method of exiting powerdown mode by driving the RPD pin low was acceptable; however, we no longer recommend this method as an option for exiting powerdown.

12.5.3.1Generating a Hardware Reset

The device will exit powerdown if RESET# is asserted. If the phase-locked loop circuitry is en- abled or if the design uses an external clock input signal rather than the on-chip oscillator, RESET# must remain low for at least 16 state times. If the design uses the on-chip oscillator, then RESET# must be held low until the oscillator and phase-locked loop circuitry have stabilized.

12.5.3.2Asserting an External Interrupt Signal

The final way to exit powerdown mode is to assert an external interrupt signal (EXTINT3:0) for at least one state time. Although EXTINT3:0 are normally sampled inputs, the powerdown cir- cuitry uses them as level-sensitive inputs. The interrupts need not be enabled to bring the device out of powerdown, but the pin must be configured as a special-function input (see “Bidirectional Port Pin Configurations” on page 7-7). Figure 12-3 shows the power-up and powerdown se- quence when using an external interrupt to exit powerdown.

When an external interrupt brings the device out of powerdown mode, the corresponding pending bit is set in the interrupt pending register. If the interrupt is enabled, the device executes the in- terrupt service routine, then fetches and executes the instruction following the IDLPD #2 instruc- tion. If the interrupt is disabled (masked), the device fetches and executes the instruction following the IDLPD #2 instruction and the pending bit remains set until the interrupt is serviced or software clears the pending bit.

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