Intel 8XC196NP, 80C196NU, Microcontroller manual Calculating Latency, Standard Interrupt Latency

8XC196NP, 80C196NU USER’S MANUAL

6.4.2Calculating Latency

The maximum latency occurs when the interrupt request occurs too late for acknowledgment fol- lowing the current instruction. The following worst-case calculation assumes that the current in- struction is not a protected instruction. To calculate latency, add the following terms:

•Time for the current instruction to finish execution (4 state times).

—If this is a protected instruction, the instruction that follows it must also execute before the interrupt can be acknowledged. Add the execution time of the instruction that follows a protected instruction.

•Time for the next instruction to execute. (The longest instruction, NORML, takes 39 state times. However, the BMOV instruction could actually take longer if it is transferring a large block of data. If your code contains routines that transfer large blocks of data, you may get a more accurate worst-case value if you use the BMOV instruction in your calculation instead of NORML. See Appendix A for instruction execution times.)

•For standard interrupts only, the response time to get the vector and force the call

—in 64-Kbyte mode, 11 state times for an internal stack or 13 for an external stack (assuming a zero-wait-state bus)

—in 1-Mbyte mode, 15 state times for an internal stack or 18 for an external stack (assuming a zero-wait-state bus)

6.4.2.1Standard Interrupt Latency

In 64-Kbyte mode, the worst-case delay for a standard interrupt is 56 state times (4 + 39 + 11 +

2)if the stack is in external memory (Figure 6-2). In 1-Mbyte mode, the worst-case delay increas- es to 61 state times (4 + 39 + 15 + 3) (Figure 6-2). This delay time does not include the time need- ed to execute the first instruction in the interrupt service routine or to execute the instruction following a protected instruction.

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