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Intel 8XC196NP manual Single Transfer Mode Ptscb, Block Transfer Mode Ptscb, Ptscount = 09H

Models: Microcontroller 80C196NU 8XC196NP

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STANDARD AND PTS INTERRUPTS

Table 6-5. Single Transfer Mode PTSCB

Unused

Unused

PTSDST (HI) = 60H

PTSDST (LO) = 00H

PTSSRC (HI) = 00H

PTSSRC (LO) = 20H

PTSCON = 85H (Mode = 100, BW = 0, SI/SU = 0, DI/DU = 1)

PTSCOUNT = 09H

6.6.4Block Transfer Mode

In block transfer mode, an interrupt causes the PTS to move a block of bytes or words from one memory location to another. See AP-445, 8XC196KR Peripherals: A User’s Point of View, for ap- plication examples with code. Figure 6-13 shows the PTS control block for block transfer modes.

In this mode, each PTS cycle consists of the transfer of an entire block of bytes or words. Because a PTS cycle cannot be interrupted, the block transfer mode can create long interrupt latency. The worst-case latency could be as high as 500 states, if you assume a block transfer of 32 words from one external memory location to another, using an 8-bit bus with no wait states. See Table 6-4 on page 6-10 for execution times of PTS cycles.

The PTSCB in Table 6-6 sets up three PTS cycles that will transfer five bytes from memory loca- tions 20–24H to 6000–6004H (cycle 1), 6005–6009H (cycle 2), and 600A–600EH (cycle 3). The source and destination are incremented after each byte transfer, but the original source address is reloaded into PTSSRC at the end of each block-transfer cycle. In this routine, the PTS always gets the first byte from location 20H.

Table 6-6. Block Transfer Mode PTSCB

Unused

PTSBLOCK = 05H

PTSDST (HI) = 60H

PTSDST (LO) = 00H

PTSSRC (HI) = 00H

PTSSRC (LO) = 20H

PTSCON = 17H (Mode = 000; DI, SI, DU, BW = 1; SU = 0)

PTSCOUNT = 03H

6-23

Image 130

Intel 8XC196NP, 80C196NU manual Single Transfer Mode Ptscb, Block Transfer Mode Ptscb, Ptscount = 09H, Ptscount = 03H

Contents

8XC196NP, 80C196NU Microcontroller User’ Manual 8XC196NP, 80C196NU Microcontroller User’s Manual Intel Corporation Contents Chapter Programming Considerations Contents Chapter Ports Programming the Serial Port EPA Functional Overview8XC196NP, 80C196NU USER’S Manual Chapter Interfacing with External Memory Appendix C Registers Glossary Index Figures 10-7 Valid EPA Input Events 13-16 Tables 10-5 Example Control Register Settings and EPA Operations 8XC196NP and 80C196NU Signals Arranged by Function Guide to This Manual Page Manual Contents Chapter Guide to this Manual8XC196NP, 80C196NU USER’S Manual Notational Conventions and Terminology AddressesItalics Units of measure Related DocumentsApplication Notes, Application Briefs, and Article Reprints Handbooks and Product InformationTitle Order Number MCS 96 Microcontroller Datasheets Commercial/Express MCS 96 Microcontroller Datasheets Automotive8XC196NP, 80C196NU USER’S Manual Intentionally Left Blank Intentionally Left Blank Technical Support World Wide WebProduct Literature Page Architectural Overview Page Chapter Architectural Overview Typical ApplicationsFeatures of the 8XC196NP and 80C196NU Device FeaturesBlock Diagram ROMCPU Control Register FileRegister Arithmetic-logic Unit Ralu Code ExecutionMemory Controller Instruction FormatInterrupt Service Multiply-accumulate 80C196NU OnlyInternal Timing Clock Circuitry 8XC196NPClock Circuitry 80C196NU 25 MHz State Times at Various Frequencies12.5 MHz 50 MHzPLLEN21 Multiplier State Time1 I/O Ports Event Processor Array EPA and Timer/CountersInternal Peripherals Serial I/O SIO PortPulse-width Modulator PWM Reducing Power ConsumptionSpecial Operating Modes Testing the Printed Circuit Board Design Considerations for 80C196NP to 80C196NU Conversions8XC196NP, 80C196NU USER’S Manual Advanced Math Features Page Chapter Advanced Math Features Enhanced Multiplication InstructionsMultiply/Accumulate Example Code Saturation ModeOperating Modes Instructions Execution TimeFractional Mode Accumulator Register ACC0x Accstat Accumulator Control and Status Register AccstatBit Function Number Mnemonic SME FME Effect of SME and FME Bit CombinationsDescription Programming Considerations Page Operand Type No. Signed Possible Values Addressing Overview of the Instruction SETOperand Type Definitions RestrictionsByte Operands BIT OperandsSHORT-INTEGER Operands Integer Operands Word OperandsDOUBLE-WORD Operands Converting Operands LONG-INTEGER OperandsQUAD-WORD Operands Conditional JumpsFloating Point Operations Extended InstructionsEST Addressing ModesIndirect Addressing Direct AddressingImmediate Addressing Definition of Temporary RegistersIndirect Addressing with Autoincrement Extended Indirect AddressingExtended Indirect Addressing with Autoincrement Short-indexed Addressing Indexed AddressingIndirect Addressing with the Stack Pointer Long-indexed AddressingZero-indexed Addressing Extended Indexed AddressingExtended Zero-indexed Addressing Design Considerations for 1-MBYTE Devices Assembly Language Addressing Mode SelectionsExtended Addressing Software Standards and ConventionsAddressing 32-bit Operands Using RegistersAddressing 64-bit Operands Linking Subroutines Software Protection Features and Guidelines Memory Partitions Page Chapter Memory Partitions Memory MAP OverviewFFH 2FH 1FH 0FH F1H F0HFFH Memory Partitions80C196NP/NU External 83C196NP ROM XC196NP and 80C196NU Memory Map Hex Description Addressing ModesProgram and Special-purpose Memory Program Memory Access for the 83C196NPExternal Memory Program Memory in Page FFHSpecial-purpose Memory Special-purpose Memory Access for the 83C196NPXC196NP and 80C196NU Special-purpose Memory Addresses Reserved Memory Locations Chip Configuration BytesPeripheral Special-function Registers SFRs Interrupt and PTS VectorsPeripheral SFRs 1F7AH 1F7EH1F7CH 1F4EHStack Pointer CPU SFRsStack Pointer SP Register File Memory AddressesGeneral-purpose Register RAM Address Description Addressing Modes Range8XC196NP CPU SFRs Address High Odd Byte Low Even Byte CPU Special-function Registers SFRsCPU SFRs 80C196NU CPU SFRs Address High Odd Byte Low Even ByteWindowing 8XC196NPHlden Selecting a WindowWSR Bit FunctionSelecting a Window of the Upper Register File Addressing a Location Through a Window Peripheral SFRs 10. WindowsBase WSR or WSR1 Value WSR Value for Upper Register File2.2 64-byte Windowing Example 11. Windowed Base Addresses2.1 32-byte Windowing Example 2.3 128-byte Windowing ExampleUsing the Linker Locator to Set Up a Window Unsupported Locations Windowing Example 8XC196NP OnlyType Base Length Alignment This listing shows the disassembled code Windowing and Addressing ModesRemapping Internal ROM 83C196NP only Fetching Instructions Accessing DataFetching Code and Data in the 1-MBYTE and 64-KBYTE Modes EpcpcFormation of Extended and Nonextended Addresses Code Fetches in the 1-Mbyte Mode Code Fetches in the 64-Kbyte ModeData Fetches in the 1-Mbyte and 64-Kbyte Modes 80C196NP and 80C196NURD# WR# Memory Configuration ExamplesExample 1 Using the 64-Kbyte Mode CE#80C196NP and 80C196NU External flash memory 12. Memory Map for the System in FigureAddress Description 80C196NP and 80C196NU UnimplementedFfffffh D70 OE# WE# Example 2 a 64-Kbyte System with Additional Data StorageRD# WR# CE# 02FFFFH13. Memory Map for the System in Figure 80C196NP and 80C196NU External RAM01FFFFH Example 3 Using 1-Mbyte ModeOE# WE# OE# WRH# WRL# RD# 80C196NP and 80C196NU External memory 14. Memory Map for the System in FigureFbffffh Standard and PTS Interrupts Page Chapter Standard and PTS Interrupts Overview of InterruptsFlow Diagram for PTS and Standard Interrupts Interrupt Signals Interrupt Signals and RegistersInterrupt and PTS Control and Status Registers Intpend Interrupt Sources and PrioritiesSpecial Interrupts PtsselUnimplemented Opcode Interrupt Controller PTS ServiceInterrupt Sources, Vectors, and Priorities Software TrapEnd-of-PTS Interrupts External Interrupt PinsMultiplexed Interrupt Sources 1.3 NMIInterrupt Latency Situations that Increase Interrupt LatencyCalculating Latency Standard Interrupt LatencyStandard Interrupt Response Time PTS Interrupt Latency Programming the Interrupts PTS Mode Execution Time in State TimesExecution Times for PTS Cycles Ptssel Programming Considerations for Multiplexed InterruptsBit Mnemonic Interrupt PTS Vector EPA0 EXTINT1 EXTINT0 OVRTM2 OVRTM1 IntmaskBit Mnemonic Interrupt Standard Vector NMI EXTINT3 EXTINT2 Modifying Interrupt PrioritiesINTMASK1 EPA3 EPA2 EPA1RET Cseg AT 0FF200CH Determining the Source of an Interrupt Interrupt Pending Intpend Register IntpendInitializing the PTS Control Blocks INTPEND1Specifying the PTS Count PWM Toggle ModePWM Remap Mode Single TransferPtssrv Selecting the PTS ModeEPA3 EPA2 EPA1 EXTINT0 OVRTM1 OVRTM2 Ptscon Single Transfer ModeAddress Ptspcb + Register Location Function PTS Single Transfer Mode Control BlockPtsdst HI Ptsdst LO Ptssrc HI Ptssrc LO Ptscon Ptscount Ptsdst Ptscb +8XC196NP, 80C196NU USER’S Manual Block Transfer Mode Ptscb Block Transfer ModeSingle Transfer Mode Ptscb Ptscount = 09HPTS Block Transfer Mode Control Block Ptsblock Ptscb +Increment the contents of Ptssrc after each byte or word Comparison of PWM Modes PWM Toggle Mode PWM Remap ModePWM Modes PTSCONST2PWM Toggle Mode Example 14. a Generic PWM WaveformPWM Toggle Mode Ptscb PTSCONST1 HI = T1 HI PTSCONST1 LO = T1 LO PTSPTR1 HI = 1FHPTSCONST1 H PTSCONST2 HPTSCONST2 L PTSCONST1 LPtscon Ptscb + Tmod16. EPA and PTS Operations for the PWM Toggle Mode Example PWM Remap Mode Example PWM Remap Mode Ptscb PTS PWM Remap Mode Control Block PTSCONST1 HI PTSCONST1 LO PTSPTR1 HI PTSPTR1 LO PtsconPTS PWM Remap Mode Control Block Register PWM Tmod18. EPA and PTS Operations for the PWM Remap Mode Example Ports Page Device I/O Ports I/O Ports OverviewBidirectional Ports Port Bits TypeBidirectional Port Pins Port Pin Special-function Associated SignalsBidirectional Port Operation Bidirectional Port Control and Status Registers8XC196NP, 80C196NU USER’S Manual Bidirectional Port Structure Logic Table for Bidirectional Ports in I/O Mode SfdirBidirectional Port Pin Configurations Control Register Values for Each Configuration Bidirectional Port Pin Configuration ExamplePort Configuration Example Bidirectional Port Considerations HZ1P2.7/CLKOUT Design Considerations for External Interrupt Inputs Eport PinsPort Pin Extended-address Signal Type EportEport Operation 10. Eport Control and Status RegistersEport Block Diagram Complementary Output Mode ResetOutput Enable Open-drain Output ModeEport Structure 12. Logic Table for Eport in Address Mode Input Mode11. Logic Table for Eport in I/O Mode Epmode Epdir EpregConfiguring Eport Pins for I/O Configuring Eport PinsConfiguring Eport Pins for Extended-address Functions 13. Configuration Register Settings for Eport PinsEport Considerations Eport Status During Instruction ExecutionDesign Considerations Page Serial I/O SIO Port Page SIO Block Diagram Serial I/O SIO Port Functional OverviewSerial Port Control and Status Registers Serial I/O Port Signals and RegistersSerial Port Signals SerialSbuftx 1FBAH P1REG 1FD4HSbufrx 1FB8H Spbaud 1FBCH,1FBDHSerial Port Modes Synchronous Mode ModeSpstatus 1FB9H Mode 0 Timing Asynchronous Modes Modes 1, 2,Serial Port Frames for Mode ModeSerial Port Frames in Mode 2 Mode 2 and 3 TimingsProgramming the Control Register Configuring the Serial Port PinsProgramming the Serial Port Programming the Baud Rate and Clock SourcePAR TB8 PRS REN PEN SpconPAR Spcon Bit FunctionSpbaud Baud Rate Spbaud Register Value Note Error Mode Mode 1, 2 Spbaud Values When Using the Internal Clock at 25 MHz8A2BH Determining Serial Port Status Baud Rate Spbaud Register Value † Error ModeEnabling the Serial Port Interrupts 8A2CHRPE/RB8 TXE SpstatusRPE/RB8 Serial I/O SIO Port Page Pulse-width Modulator Page PWM Block Diagram 8XC196NP Only PWM Functional OverviewPWM Signals and Registers PWM SignalsPWM Operation PWM Control and Status Registers8XC196NP, 80C196NU USER’S Manual E6H EnabledProgramming the Frequency and Period FFHCLK0 PWM Output Frequencies 8XC196NPPWM Output Frequencies 80C196NU CLK1 CLK0FEH Programming the Duty CycleCONREG0 CLK1 CLK0PWM xCONTROL Address DisabledClock Prescaler PWM Duty CycleEnabling the PWM Outputs PWM Output Alternate Port Function PWM Output Enabled WhenSample Calculations PWM Output Alternate FunctionsD/A Buffer Block Diagram Event Processor Array EPA Page Chapter Event Processor Array EPA EPA Functional OverviewPort Pin EPA Signals EPA and TIMER/COUNTER Signals and RegistersEPA and Timer/Counter Signals EPAEPA Control and Status Registers TIMER1 TIMER2TIMER/COUNTER Functional Overview EPA Timer/CountersCascade Mode Timer 2 Only Quadrature Clocking ModeQuadrature Mode Interface Quadrature Mode Truth Table Quadrature Mode Timing and Count EPA Channel Functional OverviewOperating in Capture Mode A Single EPA Capture/Compare ChannelEPA Simplified Input-capture Structure EPA Overruns Action Taken when a Valid Edge OccursAction taken when a valid edge occurs EPAxCON.0Preventing EPA Overruns Operating in Compare ModeGenerating a Low-speed PWM Output Generating a Medium-speed PWM Output Generating a High-speed PWM Output Programming the Timers Programming the EPA and TIMER/COUNTERSConfiguring the EPA and Timer/Counter Port Pins Generating the Highest-speed PWM OutputT1CONTROL Prescaler Divisor Resolution †Clock Source Direction Source Prescaler Resolution † T2CONTROLMode ROT ON/RT Example Control Register Settings and EPA OperationsProgramming the Capture/Compare Channels = 1 = 0 EPA xCON Address Reset State 00HROT ON/RT Capture Mode Event Compare Mode ActionCompare Mode RT Capture Mode onROT Determining Event Status Enabling the EPA InterruptsEpamask 12. EPA Interrupt Pending Epapend Register Epapend †Programming Examples for EPA Channels EPA Capture Event Program EPA PWM Output Program Unsigned char Unused Ptscon10-27 Page Minimum Hardware Considerations Page Signal Minimum Required SignalsMinimum Connections Unused Inputs I/O Port Configuration GuidePort Where to Find Configuration Information 11.1.2 I/O Port Pin ConnectionsMinimum Hardware Connections Applying and Removing Power Noise Protection TipsON-CHIP Oscillator Circuitry On-chip Oscillator CircuitExternal Crystal Connections Using AN External Clock Source External Clock ConnectionsResetting the Device Reset Timing SequenceGenerating an External Reset Internal Reset CircuitryMinimum Reset Circuit Issuing the Reset RST Instruction Issuing an Illegal Idlpd Key OperandPage Special Operating Modes Page Port Pin Signal Type Description Name Special Operating Mode Signals and RegistersOperating Mode Control Signals OncePLLEN21 Operating Mode Control and Status RegistersPort Pin Signal Type Description CCR0P2MODE 1FD1H Reducing Power ConsumptionP2DIR 1FD3H P2REG 1FD5HClock Control During Power-saving Modes 8XC196NP Idle Mode Clock Control During Power-saving Modes 80C196NUEnabling and Disabling Standby Mode Standby Mode 80C196NU onlyEntering Standby Mode Enabling and Disabling Powerdown Mode Exiting Standby ModePowerdown Mode Entering Powerdown ModeGenerating a Hardware Reset Exiting Powerdown ModeAsserting an External Interrupt Signal External RC Circuit Selecting C1 Typical Voltage on the RPD Pin While Exiting Powerdown Once Mode Reserved Test Modes 80C196NU onlyC196NU Clock Modes PLLEN2 PLLEN1Page Interfacing with External Memory Page Internal and External Addresses Example of Internal and External AddressesBit Multiplexed Bus Mode External Memory Interface SignalsExternal Memory Interface Signals Bit Demultiplexed ModeALE Bytes AccessedDescription Multiplexed With BHE#Inst Name Type Description Multiplexed WithEA# ReadyWRL# CHIP-SELECT UnitWRH# Chip-select Registers Register Address Description MnemonicDefining Chip-select Address Ranges Addrcom Address Reset StateRegister Address Addrmsk Address Reset State Register Address Reset ValueAddress Mbyte Kbyte Bytes Base Addresses for Several Sizes of the Address RangeFFB00H FFE00H FFD00H FFF00H WS1 WS0 Buscon Address Reset StateControlling Wait States, Bus Width, and Bus Multiplexing Wait StatesChip-select Unit Initial Conditions BUSCONx Addresses and Reset ValuesInitializing the Chip-select Registers Example of a Chip-select Setup Uart Chip ContentsSram BusconResults for the Chip-select Example Chip Configuration Registers and Chip Configuration BytesChip Address Size Number Contents Addrcom AddrmskWS1 WS0 Demux BHE# CCR0WS0 WS1 Remap MODE64 CCR1Remap 13-17 BUS Width and Multiplexing Bit Demultiplexed Bus Bit Multiplexed BusALE ALE Bit Demultiplexed BusBit Multiplexed Bus 13.5.1 a 16-bit Example System 13.5.2 16-bit Bus Timings CS#Clkout ALE RD#13.5.3 8-bit Bus Timings A190 Address AD158 High Address Wait States Ready Control Comparison of Multiplexed and Demultiplexed BusesBus Description Demultiplexed Bus ns† Multiplexed Bus ns† 11. Ready Signal Timing Definitions Symbol DefinitionReady ALE BHE#, Inst14. Ready Timing Diagram Demultiplexed Mode 8XC196NP 15. Ready Timing Diagram Demultiplexed Mode 80C196NU BUS-HOLD ProtocolSymbol Parameter 12. HOLD#, HLDA# Timing DefinitionsDisabling the Bus-hold Protocol Enabling the Bus-hold ProtocolHold Latency 13. Maximum Hold Latency Regaining Bus ControlWRITE-CONTROL Modes Bus Cycle TypeBHE# WRH# 14. Write Signals for Standard and Write Strobe ModesALE WR# WRL# Bus Word/Byte Standard Write Strobe18. Decoding WRL# and WRH# RD# WRH# WRL# System BUS AC Timing SpecificationsWE# OE# 20. Multiplexed System Bus Timing 8XC196NP 21. Multiplexed System Bus Timing 80C196NU 22. Demultiplexed System Bus Timing 8XC196NP Deferred Bus-cycle Mode 80C196NU Only 23. Demultiplexed System Bus Timing 80C196NU24. Deferred Bus-cycle Mode Timing Diagram 80C196NU AC Timing Definitions Explanation of AC Symbols15. AC Timing Symbol Definitions Signals ConditionsSymbol Definition 8XC196Nx Meets These Specifications 13-44 13-45 Page Instruction Set Reference Page Appendix a Instruction SET Reference Table A-1. Opcode Map Left Half OpcodeTable A-1. Opcode Map Right Half Value of Bits Shifted Off Table A-2. Processor Status Word PSW FlagsMnemonic Description Instruction Quotient Stored Flag Set if Quotient isSymbol Description Table A-4. PSW Flag Setting SymbolsInstruction Jumps to Destination if Continues if Table A-5. Operand Variables Variable DescriptionMnemonic Operation PSW Flag SettingsTable A-6. Instruction Set C V VT STDest ← Dest and SRC Instruction FormatAndb Bmov PTRS, CntregDest Mnemonic Operation Instruction FormatCount ← Count PC ← DestClear WORD. Clears the value Compare BYTES. Subtracts the source DIV Dest MOD SRC← Dest MOD SRC Djnz Decrement and Jump if not ZeroDpts Disable Peripheral Transaction Djnzw Decrement and Jump if not ZeroDstptr ← Ptrs + Dstptr ← Srcptr Ptrs ← Srcptr + Ebmovi Extended Interruptable Block PTRS, CntregCount ← Cntreg EBROnto the stack, then adds to the program Epts Enable Peripheral Transaction ELDSRC, Dest EXT SIGN-EXTEND Integer Into LongExtb SIGN-EXTEND SHORT-INTEGER Into ExtbIncrement WORD. Increments the value Word operand by Mnemonic Operation Instruction Format JGE Jump if Signed Greater than orJGT JLE Jump if Signed Less than or EqualNegative flag is set, this instruction adds JNH JNV Jump if Overflow Flag is ClearJnvt Jump if OVERFLOW-TRAP Flag is JnvtJVT Jump if OVERFLOW-TRAP Flag is SET JVTKbyte mode Mbyte modeMUL MulbMulu MuluNEG Dest ← Dest PSW Flag SettingsMulub Negate INTEGER. Negates the valueMnemonic Dest ← not DestDest ← Dest or SRC ORBINTMASK1/WSR ← SP PSW/INTMASK ← SPSP ← PSW/INTMASK PSW/INTMASK ← SP ← INTMASK1/WSR INTMASK1 ←RST ScallWreg,#count Shll SHRRange of 0 to 31 1FH, inclusive. If Shral Arithmetic Right Shift Double ShralShrl Logical Right Shift DOUBLE-WORD SkipRightmost operand SUBSubc SubbSubc Subtract Words with Borrow DEST, SRC Subcb Subtract Bytes with Borrow DEST, SRCTijmp TBASE, INDEX, #MASK Index and #MASK = Offset × Offset + Tbase = Dest PC ← DestMnemonic SRCXOR Dest ← Dest XOR SRCClrb Notb Negb Table A-7. Instruction OpcodesHex Code Instruction Mnemonic Decb Extb Incb Shrb Shlb ShrabHex Code Instruction SET Reference 8XC196NP, 80C196NU USER’S Manual ST Direct ELD Indirect Arithmetic Group Direct Immediate Indirect Indexed Mnemonic Table A-8. Instruction Lengths and Hexadecimal OpcodesSubc Subcb Logical Direct Immediate Indirect Opcode Length Stack Direct Immediate Indirect Indexed MnemonicPOP Popa Popf Push Pusha Pushf Ebmovi ELD Eldb EST Estb Data Direct ImmediateExtended Direct ImmediateCall Direct Immediate Jump Direct ImmediateEBR Ejmp Lcall RETDjnz Djnzw JBC JGE JGT JLE JLT JNC JNE JNH Jnst JNV Jnvt JST JVTSpecial Mnemonic Direct Immediate Indirect Shift Mnemonic Direct Immediate Indirect IndexedLength Opcode PTSNormal Autoinc Short Long Reg Mem Table A-9. Instruction Execution Times in State TimesArithmetic Group Indirect Mem RegDIV Divb Divu Divub Mnemonic Direct Immed Normal Autoinc Short Long Reg MemLogical Normal Autoinc Short Stack Register IndirectReg Mem Indexed Mnemonic Data Mnemonic Extended-indirect NormalExtended-indexed Autoinc Short Long Reg MemMnemonic Direct Immed Ljmp Sjmp TijmpIndirect Indexed Mnemonic Direct Immed Autoinc Short LongShift Conditional JumpMnemonic Short-Indexed Mnemonic DirectNOP RST Setc Skip Special Mnemonic Direct Immed Indirect IndexedClrc Clrvt Idlpd Immed Indirect IndexedPage Signal Descriptions Page Functional Groupings of Signals Table B-1 XC196NP and 80C196NU Signals Arranged by FunctionFigure B-1 XC196NP 100-lead Sqfp Package X8XC196NPFigure B-2 XC196NP 100-lead QFP Package Figure B-3 C196NU 100-lead Sqfp Package X8XC196NUFigure B-4 C196NU 100-lead QFP Package Table B-2. Description of Columns of Table B-3 Signal DescriptionsTable B-3. Signal Descriptions Column Heading Description NameByte High Enable† WRH# BREQ#EPORT.30 EXTINT30HOLD# VSSName Type Description PLLEN1 PLLEN2VSS if either of the following conditions are true Asserted only during external memory writes RESET# NP/NU Default ConditionsTable B-4. Definition of Status Symbols RESET#ALE WK0 Ready WK1 RESET# RPDWK1 EPORT.30 BHE# WK1Registers Page CPU EPA Chip ConfigurationTable C-1. Modules and Related Registers InterruptsTable C-2. Register Name, Address, and Reset Status EPA3TIME EPA3CONEPA2TIME 1FD6H Xxxx P1REGXxxx Spbaud WSR1 NUACC0x Table C-3. ACC0x Addresses and Reset ValuesACC0x Accstat AccstatTable C-4. Effect of SME and FME Bit Combinations SME FMEADDRCOMx Table C-5. ADDRCOMx Addresses and Reset ValuesAddrcom Address ADDRMSKx Address Table C-6 Reset State Table C-6. ADDRMSKx Addresses and Reset ValuesADDRMSKx BUSCONx Table C-7. BUSCONx Addresses and Reset ValuesBuscon Address CCR0 CCR0CCR1 CCR1CONREG0 CONREG0Epdir PIN3 PIN2 PIN1 PIN0Epmode EpmodeEppin XXHEpreg X0HEpamask EpamaskEpapend EpapendEPAxCON EPA xCON AddressEPAxCON Address Table C-8 Bit FunctionBit Function Number Table C-8. EPAxCON Addresses and Reset Values Register Address Reset ValueTable C-9. EPAxTIME Addresses and Reset Values EPAxTIMEIntmask IntmaskFF203EH EXTINT3 INTMASK1FF203CH EXTINT2 Intpend IntpendINTPEND1 INTPEND1Ffffh OnesregOnesreg 150 One These bits are always equal to FfffhXDIR Address Table C-10. PxDIR Addresses and Reset ValuesPxDIR PIN7 PIN6 PIN5 PIN4 PIN3 PIN2 PIN1 PIN0Table C-12. Special-function Signals for Ports Table C-11. PxMODE Addresses and Reset ValuesPxMODE XPIN Address Table C-13. PxPIN Addresses and Reset ValuesPxPIN Bit NumberPxREG Address Table C-14 Table C-14. PxREG Addresses and Reset ValuesPxREG P1REG 1FD4H FFH P2REG 1FD5H P3REG 1FDCH P4REG 1FDDHPSW PSWPSE PSW Bit Function Number MnemonicPtssel PtsselPtssrv FF200AH EXTINT1Table C-15. PWMxCONTROL Addresses and Reset Values PWMxCONTROLSbufrx SbufrxData Received Sbuftx SbuftxData to Transmit Xxxxh Spbaud SpbaudBaud Rate Spbaud Register Value Note Error Mode Mode 1, 2Spcon SpconSpstatus T1CONTROL T1CONTROLT2CONTROL T2CONTROLTable C-17. TIMERx Addresses and Reset Values TIMERxTimer Address Register Memory 00E0-00FFH WSRByte Windows Mnemonic LocationRegister Memory 00E0-00FFH 00C0-00FFH P4DIR 1FDBH 7EH 00FBH 3FH 00DBH 1FH P4MODE 1FD9H TIMER1 †TIMER2 † PWM1CONTROL 1FB2H 7DHWSR1 Register Memory 0060-007FH 0040-007FH Mnemonic Location0060-007FH 0040-007FH Mnemonic Location Spbaud 1FBCH 7DH PWM0CONTROL 1FB0H 7DHSbuftx 1FBAH 7DH Spcon 1FBBH 7DHZeroreg Zeroreg150 Zero This register is always equal to zero Page Glossary Page Glossary DOUBLE-WORD FET ISR PIC PLL PTS SFR Uart Index Page Index Index-2 Index-3 Index-4 Index-5 Index-6 Index-7 Index-8 Index-9 Index-10 Index-11 Index-12