Index-6

8XC196NP, 80C196NU USER’S MANUAL
JNC instruction, A-2, A-5, A-24, A-51, A-58,	Miller effect, 11-7
A-66	Mode 0, SIO, 8-4, 8-5
JNE instruction, A-2, A-5, A-24, A-51, A-58, A-66	Mode 1, SIO, 8-5, 8-6
JNH instruction, A-2, A-5, A-25, A-51, A-58,	Mode 2, SIO, 8-5, 8-7, 8-8
A-66	Mode 3, SIO, 8-5, 8-7, 8-8
JNST instruction, A-2, A-5, A-25, A-51, A-58,	MODE64 bit, 5-23
A-66	MUL instruction, 3-1, A-29, A-52, A-54, A-61
JNV instruction, A-2, A-5, A-25, A-51, A-58,	MULB instruction, A-29, A-30, A-52, A-54, A-61
A-66	Multiplication instructions
JNVT instruction, A-2, A-5, A-26, A-51, A-58,	multiply/accumulate example code, 3-2
A-66	See also MUL instruction, MULU instruction
JST instruction, A-3, A-5, A-26, A-51, A-58, A-66	Multiprocessor communications
Jump instructions, A-64	SIO port, 8-7, 8-8
conditional, A-5, A-58, A-66	MULU instruction, 3-1, A-3, A-30, A-48, A-49,
unconditional, A-57	A-52, A-54, A-61
JV instruction, A-3, A-5, A-26, A-51, A-58, A-66	MULUB instruction, A-3, A-31, A-48, A-49,
JVT instruction, A-3, A-5, A-27, A-51, A-58, A-66	A-54, A-61

Latency‚ See bus-hold protocol‚ interrupts LCALL instruction, A-3, A-27, A-52, A-57, A-65 LD instruction, A-2, A-27, A-50, A-56, A-63 LDB instruction, A-2, A-28, A-50, A-56, A-63 LDBSE instruction, A-3, A-28, A-50, A-56, A-63 LDBZE instruction, A-3, A-28, A-50, A-56, A-63 Level-sensitive input, B-6

Literature, 1-11

LJMP instruction, A-2, A-28, A-52, A-57, A-64 Logical instructions, A-54, A-61 LONG-INTEGER, defined, 4-4

Lookup tables, software protection, 4-14

Manual contents, summary, 1-1 Manuals, online, 1-10

Math features, 3-1–3-6 Measurements, defined, 1-5 Memory bus, 2-5

Memory configuration, examples, 5-27–5-32 Memory controller, 2-3, 2-5

Memory map, 5-3

Example of 1-Mbyte mode, 5-32 Example of 64-Kbyte mode, 5-28, 5-30

Memory, external, 13-1–13-45 interface signals, 13-2

Memory, reserved, 5-6, 5-7 Microcode engine, 2-3

Naming conventions, 1-3–1-4

NEG instruction, A-2, A-31, A-47, A-54, A-61 Negative (N) flag, A-4, A-5, A-22, A-23, A-24 NEGB instruction, A-2, A-31, A-47, A-54, A-61 NMI, 6-3, 6-4, 6-6, B-9

and bus-hold protocol, 13-33 hardware considerations, 6-6

Noise, reducing, 7-1, 7-4, 11-4, 11-5, 11-6 Nonextended addressing, 5-23

NOP instruction, 4-14, A-3, A-31, A-52, A-59, A-67

two-byte‚ See SKIP instruction

NORML instruction, 4-5, A-3, A-32, A-47, A-59, A-66

NOT instruction, A-2, A-32, A-47, A-54, A-61 Notational conventions, 1-3–1-4

NOTB instruction, A-2, A-32, A-47, A-54, A-61 Numbers, conventions, 1-4

ONCE, 12-1, B-9

ONCE mode, 2-12, 12-12 entering, 12-12 exiting, 12-12

Opcodes, A-47

EE, and unimplemented opcode interrupt, A-3, A-52

FE, and signed multiply and divide, A-3

Microcontroller, 80C196NU, 8XC196NP specifications

The Intel 8XC196NP and 80C196NU microcontrollers are part of Intel's renowned 16-bit microcontroller series that gained popularity in the 1980s and 1990s for embedded systems applications. Designed for a variety of applications, these microcontrollers are characterized by their robust performance, versatility, and industry-standard architecture.

The 8XC196NP features an enhanced instruction set with over 100 instructions, allowing for efficient code execution. It operates at clock speeds up to 16 MHz, which contributes to improved performance in time-sensitive applications. The microcontroller is equipped with a 16-bit data bus, enabling more efficient data handling compared to its 8-bit predecessors, thus accommodating complex algorithms and large data sets.

In terms of memory architecture, the 8XC196NP supports an addressable memory space of up to 64 KB of program memory and 64 KB of data memory. This configuration provides sufficient space for large applications while ensuring fast data access. The microcontroller includes integrated features such as timers, serial I/O capabilities, and interrupt processing, which enhance its functionality for real-time applications and control mechanisms.

The 80C196NU, on the other hand, is designed for lower power operation, making it suitable for battery-powered devices. This microcontroller maintains similar features to the 8XC196NP while offering advancements that support low-power consumption. The 80C196NU can also function in a range of temperature environments, making it adaptable for industrial applications.

Both the 8XC196NP and 80C196NU support external memory interfacing, allowing designers to expand the system's capability by connecting additional ROM and RAM. This flexibility makes them appealing for developing complex systems, such as motor controls, industrial automation, and consumer electronics.

Another standout feature of these microcontrollers is their built-in debugging capabilities. Intel provided hardware and software tools that enabled developers to test and troubleshoot their applications effectively, reducing the development time and increasing reliability.

Overall, the Intel 8XC196NP and 80C196NU microcontrollers stand out for their dependability, versatility, and performance, contributing significantly to the evolution of embedded system design. Their legacy continues to influence modern microcontroller technology, ensuring their relevance in a wide array of applications today.

Intel 80C196NU, 8XC196NP, Microcontroller manual Index-6

Models: Microcontroller 80C196NU 8XC196NP

8XC196NP, 80C196NU USER’S MANUAL

Index-6

Microcontroller, 80C196NU, 8XC196NP specifications