Intel 8XC196NP, 80C196NU, Microcontroller manual EPA Interrupt Pending Epapend Register, Epapend †

EVENT PROCESSOR ARRAY (EPA)

EPA_PEND†	Address:	1F9EH
	Reset State:	AAH

When hardware detects a pending EPA3:0 overrun interrupt (OVR3:0), it sets the corresponding bit in the EPA interrupt pending (EPA_PEND) register. OVR0 and OVR1 are multiplexed to share one bit (OVR0_1) in the INT_PEND1 register. Similarly, OVR2 and OVR3 are multiplexed to share another bit

(OVR2_3) in the INT_PEND1 register.

7

— OVR3 — OVR2

0

— OVR1 — OVR0

Bit	Function
Number
7, 5, 3, 1	Reserved. These bits are undefined.
6, 4, 2, 0	Any set bit indicates that the corresponding overrun interrupt source is pending.

†This register was called EPA_STAT in previous documentation for the 8XC196NP.

Figure 10-12. EPA Interrupt Pending (EPA_PEND) Register

The EPA interrupt pending register, EPA_PEND, has the same bit structure as the EPA_MASK register. EPA_PEND is similar to an interrupt pending register in that it shows the status of the individual capture/compare overrun interrupts. The bits in EPA_PEND can be polled to deter- mine the exact source of an OVR0_1 or OVR2_3 interrupt. However, hardware does not clear status bits in this register when it vectors to the interrupt service routine for an interrupt pair (OVR0_1, OVR2_3) so the user’s code must clear the register. Instead it clears the OVR0_1 or OVR2_3 bit in the INT_MASK register. Also, software cannot generate an interrupt by setting a bit in EPA_PEND.

10.7.1 Using Software to Service the Multiplexed Overrun Interrupts

The multiplexed overrun interrupts should normally be serviced by interrupt service routines be- cause the PTS cannot determine the exact source of the interrupt. When an OVR0_1 or OVR2_3 occurs, the user’s software service routine can poll the bits of the EPA_PEND register, which has a bit for each overrun source, to determine which of the four capture/compare channels caused the interrupt. The individual sources can be masked by bits in the EPA_MASK register.

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