Intel 8XC196NP, 80C196NU, Microcontroller manual Generating a High-speed PWM Output

8XC196NP, 80C196NU USER’S MANUAL

The maximum output frequency depends upon the total interrupt latency and interrupt-service ex- ecution time. As additional EPA channels and the other functions of the microcontroller are used, the maximum PWM frequency decreases because the total interrupt latency and interrupt-service execution time increases. To determine the maximum, medium-speed PWM frequency in your system, calculate your system's worst-case interrupt latency and worst-case interrupt-service ex- ecution time, and then add them together. The worst-case interrupt latency is the total latency of all the interrupts (both normal and PTS) used in your system. The worst-case interrupt-service execution time is the total execution time of all interrupt service routines and PTS cycles.

Assume a system with a single EPA channel, a single enabled interrupt, and PTS service. Also assume that the PTS is initialized and that the duty cycle and frequency are fixed. The worst-case interrupt latency for a single-interrupt system with PTS service is 43 state times (see “PTS Inter- rupt Latency” on page 6-9). The PTS cycle execution time in PWM toggle mode is 15 state times (Table 6-4 on page 6-10). Therefore, a single capture/compare channel can be updated every 58 state times (43 + 15). Each PWM period requires two updates (one setting and one clearing), so the execution time for a PWM period equals 116 state times. When the input frequency on XTAL1 is 25 MHz and the phase-locked loop is disabled on the 80C196NU, the PWM period is 9.27 µs and the maximum PWM frequency is 107.8 kHz.

10.4.2.3Generating a High-speed PWM Output

You can generate a high-speed, pulse-width modulated output with a pair of EPA channels and the PTS set up in PWM remap mode. “PWM Remap Mode Example” on page 6-32 describes how to configure the EPA and PTS. The remap bit (bit 8) must be set in EPA1_CON (to pair EPA0 and EPA1) or EPA3_CON (to pair EPA2 and EPA3). One channel must be configured to set the out- put; the other, to clear it. At the set (or clear) time, the PTS reads the old time value from EPAx_TIME, adds to it the PWM period constant, and returns the new value to EPAx_TIME. Set and clear times can be programmed to differ by as little as one timer count, resulting in very nar- row pulses. Once started, this method requires no CPU intervention unless you need to change the output frequency. The method uses a single timer/counter. The timer/counter is not interrupted during this process, so other EPA channels can also use it if they do not reset it.

To determine the maximum, high-speed PWM frequency in your system, calculate your system's worst-case interrupt latency and then double it. The worst-case interrupt latency is the total la- tency of all the interrupts (both normal and PTS) used in your system.

Assume a system that uses a pair of remapped EPA channels (i.e., EPA0 and 1 or EPA3 and 4), two enabled interrupts, and PTS service. Also assume that the PTS is initialized and that the duty cycle and frequency are fixed. The worst-case interrupt latency for a single-interrupt system with PTS service is 43 state times (see “PTS Interrupt Latency” on page 6-9). In this mode, the maxi- mum period equals twice the PTS latency. Therefore, the execution time for a PWM period equals 86 state times. When the input frequency on XTAL1 is 25 MHz and the phase-locked loop is dis- abled on the 80C196NU, the PWM period is 6.88 µs and the maximum PWM frequency is 145.3 kHz.

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