Intel Microcontroller, 80C196NU manual Chip-select Registers, Register Address Description Mnemonic

8XC196NP, 80C196NU USER’S MANUAL

Table 13-3. Chip-select Registers

Register	Address	Description
Mnemonic
ADDRCOM0	1F40H	Address Compare Register
ADDRCOM1	1F48H	This 16-bit register holds the upper 12 bits of the base
ADDRCOM2	1F50H
		address of the address range assigned to CSx#.
ADDRCOM3	1F58H
ADDRCOM4	1F60H
ADDRCOM5	1F68H
ADDRMSK0	1F42H	Address Mask Register
ADDRMSK1	1F4AH	This register determines the size of the address range
ADDRMSK2	1F52H
		(256 bytes–1 Mbyte).
ADDRMSK3	1F5AH
ADDRMSK4	1F62H
ADDRMSK5	1F6AH
BUSCON0	1F44H	Bus Control Register
BUSCON1	1F4CH	This register determines the bus configuration for external
BUSCON2	1F54H
		accesses to the address range assigned to CSx#. The
BUSCON3	1F5CH
		bus parameters are 8- or 16-bit bus width, multiplexed or
BUSCON4	1F64H
		demultiplexed address/data lines, and the number of wait
BUSCON5	1F6CH
		states inserted into each bus cycle.

Figure 13-1 illustrates the device’s calculation of a chip-select output CS x# for a given external memory address. The 12 most-significant bits of the external address are compared (XORed) bit- wise with the 12 least-significant bits (BASE19:8) of the ADDRCOMx register. If all of the bits match, CSx# is asserted. Additionally, if some bits do not match, CSx# is still asserted if, for each non-matching bit in ADDRCOMx, the corresponding bit in ADDRMSKx is cleared. The 12 least- significant bits are named MASK19:8 for their function in masking bits BASE19:8.

External Address						ADDRCOMx				ADDRMSKx
19	8	7	0	15		12 11		0 15		12 11		0
					R • •￿ •￿R		BASE19:0		R • •￿ •￿R			MASK19:0
bit x							bit x				bit x

CSx#

A2386-02

Figure 13-1. Calculation of a Chip-select Output

13-6