Intel 8XC196NP manual Comparison of Multiplexed and Demultiplexed Buses, Wait States Ready Control

8XC196NP, 80C196NU USER’S MANUAL

13.5.4 Comparison of Multiplexed and Demultiplexed Buses

This section compares the timings for multiplexed and demultiplexed buses. A 16-bit bus is used for the comparison. “8-bit Bus Timings” on page 13-24 compares the 8-bit and 16-bit buses.

In a multiplexed system, where AD15:0 carry both address and data, bus activities are time-com- pressed in comparison with a demultiplexed system, where the address and data have separate lines (A19:0 and AD15:0). The compression is reflected in differences in specifications for the demultiplexed and multiplexed bus. Table 13-10 lists several bus specifications and their values for demultiplexed and multiplexed buses. The data shows that the demultiplexed bus can accom- modate slower memory devices. (See “System Bus AC Timing Specifications” on page 13-36 for a complete list of AC timing definitons.)

Table 13-10. Comparison of AC Timings for Demultiplexed and Multiplexed 16-bit Buses

Bus	Description	Demultiplexed Bus (ns)†	Multiplexed Bus (ns)†
Spec.
TRLDV	Max. time from RD# asserted to	2t – 25	t – 20
	valid input data on the bus.
TAVDV	Max. time from A19:0 and CSx#	4t – 50	3t – 40
	valid to valid input data on the bus.
TRHDZ	Max. time from RD# deasserted	t	t
	until data bus is at high impedance.
TWLWH	Minimum time that WR# is	2t – 10	t – 5
	asserted.
TQVWH	Minimum time from valid data on	3t – 33	t – 15
	the bus to WR# deasserted.

†Consult the device datasheet for the latest specifications.

13.6 WAIT STATES (READY CONTROL)

An external device can use the READY input to request wait states in addition to the wait states that are generated internally by the 8XC196Nx device. When an address is placed on the bus for an external bus cycle, the external device can pull the READY signal low to indicate it is not ready. In response, the bus controller inserts wait states to lengthen the bus cycle until the external device raises the READY signal. Each wait state adds one CLKOUT period (i.e., one state time or 2t) to the bus cycle.

The READY signal is effective for all bus cycles, including the CCB0 fetch (which has three in- ternal wait states). Bits WS0 and WS1 in CCB0 specify the wait states for the CCB1 fetch. There- after, the WS0 and WS1 bits in the BUSCONx registers control the wait states, and the READY signal can be used to insert additional wait states. (See “Controlling Wait States, Bus Width, and Bus Multiplexing” on page 13-10.)

13-26