8XC196NP, 80C196NU Microcontroller User’ Manual
 8XC196NP, 80C196NU Microcontroller User’s Manual
 Intel Corporation
 Contents
 Chapter Programming Considerations
 Contents
 Chapter Ports
 EPA Functional Overview
Programming the Serial Port
 8XC196NP, 80C196NU USER’S Manual
 Chapter Interfacing with External Memory
 Appendix C Registers Glossary Index
 Figures
 10-7 Valid EPA Input Events
 13-16
 Tables
 10-5 Example Control Register Settings and EPA Operations
 8XC196NP and 80C196NU Signals Arranged by Function
 Guide to This Manual
Page
 Chapter Guide to this Manual
Manual Contents
 8XC196NP, 80C196NU USER’S Manual
 Addresses
Notational Conventions and Terminology
 Italics
 Related Documents
Units of measure
 Application Notes, Application Briefs, and Article Reprints
Handbooks and Product Information
Title Order Number
 MCS 96 Microcontroller Datasheets Automotive
MCS 96 Microcontroller Datasheets Commercial/Express
 8XC196NP, 80C196NU USER’S Manual
 Intentionally Left Blank
 Intentionally Left Blank
 Technical Support
World Wide Web
Product Literature
Page
 Architectural Overview
Page
 Typical Applications
Chapter Architectural Overview
 Block Diagram
Device Features
Features of the 8XC196NP and 80C196NU
ROM
 Register File
CPU Control
 Code Execution
Register Arithmetic-logic Unit Ralu
 Instruction Format
Memory Controller
 Multiply-accumulate 80C196NU Only
Interrupt Service
 Clock Circuitry 8XC196NP
Internal Timing
 Clock Circuitry 80C196NU
 12.5 MHz
State Times at Various Frequencies
25 MHz
50 MHz
 Multiplier State Time
PLLEN21
 Internal Peripherals
Event Processor Array EPA and Timer/Counters
1 I/O Ports
Serial I/O SIO Port
 Pulse-width Modulator PWM
Reducing Power Consumption
Special Operating Modes
 Design Considerations for 80C196NP to 80C196NU Conversions
Testing the Printed Circuit Board
 8XC196NP, 80C196NU USER’S Manual
 Advanced Math Features
Page
 Enhanced Multiplication Instructions
Chapter Advanced Math Features
 Operating Modes
Saturation Mode
Multiply/Accumulate Example Code
Instructions Execution Time
 Fractional Mode
 Accumulator Register ACC0x
 Accstat
Accumulator Control and Status Register Accstat
Bit Function Number Mnemonic
 SME FME
Effect of SME and FME Bit Combinations
Description
 Programming Considerations
Page
 Operand Type Definitions
Overview of the Instruction SET
Operand Type No. Signed Possible Values Addressing
Restrictions
 Byte Operands
BIT Operands
SHORT-INTEGER Operands
 Integer Operands
Word Operands
DOUBLE-WORD Operands
 QUAD-WORD Operands
LONG-INTEGER Operands
Converting Operands
Conditional Jumps
 Extended Instructions
Floating Point Operations
 Addressing Modes
EST
 Immediate Addressing
Direct Addressing
Indirect Addressing
Definition of Temporary Registers
 Indirect Addressing with Autoincrement
Extended Indirect Addressing
Extended Indirect Addressing with Autoincrement
 Indirect Addressing with the Stack Pointer
Indexed Addressing
Short-indexed Addressing
Long-indexed Addressing
 Zero-indexed Addressing
Extended Indexed Addressing
Extended Zero-indexed Addressing
 Extended Addressing
Assembly Language Addressing Mode Selections
Design Considerations for 1-MBYTE Devices
Software Standards and Conventions
 Addressing 32-bit Operands
Using Registers
Addressing 64-bit Operands
 Linking Subroutines
 Software Protection Features and Guidelines
 Memory Partitions
Page
 Memory MAP Overview
Chapter Memory Partitions
 F0H
FFH 2FH 1FH 0FH F1H
 FFH
Memory Partitions
80C196NP/NU External 83C196NP ROM
 Hex Description Addressing Modes
XC196NP and 80C196NU Memory Map
 External Memory
Program Memory Access for the 83C196NP
Program and Special-purpose Memory
Program Memory in Page FFH
 Special-purpose Memory
Special-purpose Memory Access for the 83C196NP
XC196NP and 80C196NU Special-purpose Memory Addresses
 Peripheral Special-function Registers SFRs
Chip Configuration Bytes
Reserved Memory Locations
Interrupt and PTS Vectors
 Peripheral SFRs
 1F7CH
1F7EH
1F7AH
1F4EH
 CPU SFRs
Stack Pointer
 General-purpose Register RAM
Register File Memory Addresses
Stack Pointer SP
Address Description Addressing Modes Range
 CPU SFRs
CPU Special-function Registers SFRs
8XC196NP CPU SFRs Address High Odd Byte Low Even Byte
80C196NU CPU SFRs Address High Odd Byte Low Even Byte
 8XC196NP
Windowing
 WSR
Selecting a Window
Hlden
Bit Function
 Selecting a Window of the Upper Register File
 Addressing a Location Through a Window
 Base WSR or WSR1 Value WSR Value for
10. Windows
Peripheral SFRs
Upper Register File
 2.1 32-byte Windowing Example
11. Windowed Base Addresses
2.2 64-byte Windowing Example
2.3 128-byte Windowing Example
 Unsupported Locations Windowing Example 8XC196NP Only
Using the Linker Locator to Set Up a Window
 Type Base Length Alignment
 Windowing and Addressing Modes
This listing shows the disassembled code
 Remapping Internal ROM 83C196NP only
 Fetching Code and Data in the 1-MBYTE and 64-KBYTE Modes
Accessing Data
Fetching Instructions
Epcpc
 Formation of Extended and Nonextended Addresses
 Code Fetches in the 64-Kbyte Mode
Code Fetches in the 1-Mbyte Mode
 80C196NP and 80C196NU
Data Fetches in the 1-Mbyte and 64-Kbyte Modes
 Example 1 Using the 64-Kbyte Mode
Memory Configuration Examples
RD# WR#
CE#
 Address Description
12. Memory Map for the System in Figure
80C196NP and 80C196NU External flash memory
80C196NP and 80C196NU Unimplemented
 RD# WR# CE#
Example 2 a 64-Kbyte System with Additional Data Storage
Ffffffh D70 OE# WE#
02FFFFH
 80C196NP and 80C196NU External RAM
13. Memory Map for the System in Figure
 01FFFFH
Example 3 Using 1-Mbyte Mode
OE# WE# OE# WRH# WRL# RD#
 80C196NP and 80C196NU External memory
14. Memory Map for the System in Figure
Fbffffh
 Standard and PTS Interrupts
Page
 Overview of Interrupts
Chapter Standard and PTS Interrupts
 Flow Diagram for PTS and Standard Interrupts
 Interrupt Signals
Interrupt Signals and Registers
Interrupt and PTS Control and Status Registers
 Special Interrupts
Interrupt Sources and Priorities
Intpend
Ptssel
 Interrupt Sources, Vectors, and Priorities
Interrupt Controller PTS Service
Unimplemented Opcode
Software Trap
 Multiplexed Interrupt Sources
External Interrupt Pins
End-of-PTS Interrupts
1.3 NMI
 Situations that Increase Interrupt Latency
Interrupt Latency
 Standard Interrupt Latency
Calculating Latency
 Standard Interrupt Response Time PTS Interrupt Latency
 Programming the Interrupts
PTS Mode Execution Time in State Times
Execution Times for PTS Cycles
 Ptssel
Programming Considerations for Multiplexed Interrupts
Bit Mnemonic Interrupt PTS Vector
 EPA0 EXTINT1 EXTINT0 OVRTM2 OVRTM1
Intmask
Bit Mnemonic Interrupt Standard Vector
 INTMASK1
Modifying Interrupt Priorities
NMI EXTINT3 EXTINT2
EPA3 EPA2 EPA1
 RET Cseg AT 0FF200CH
 Determining the Source of an Interrupt
 Intpend
Interrupt Pending Intpend Register
 INTPEND1
Initializing the PTS Control Blocks
 PWM Remap Mode
PWM Toggle Mode
Specifying the PTS Count
Single Transfer
 Ptssrv
Selecting the PTS Mode
EPA3 EPA2 EPA1 EXTINT0 OVRTM1 OVRTM2
 Ptscon
Single Transfer Mode
Address Ptspcb +
 Ptsdst HI Ptsdst LO Ptssrc HI Ptssrc LO Ptscon Ptscount
PTS Single Transfer Mode Control Block
Register Location Function
Ptsdst Ptscb +
 8XC196NP, 80C196NU USER’S Manual
 Single Transfer Mode Ptscb
Block Transfer Mode
Block Transfer Mode Ptscb
Ptscount = 09H
 Ptsblock Ptscb +
PTS Block Transfer Mode Control Block
 Increment the contents of Ptssrc after each byte or word
 PWM Modes
PWM Toggle Mode PWM Remap Mode
Comparison of PWM Modes
PTSCONST2
 14. a Generic PWM Waveform
PWM Toggle Mode Example
 PTSCONST1 HI = T1 HI PTSCONST1 LO = T1 LO PTSPTR1 HI = 1FH
PWM Toggle Mode Ptscb
 PTSCONST2 L
PTSCONST2 H
PTSCONST1 H
PTSCONST1 L
 Tmod
Ptscon Ptscb +
 16. EPA and PTS Operations for the PWM Toggle Mode Example
 PWM Remap Mode Example
 PWM Remap Mode Ptscb
 PTSCONST1 HI PTSCONST1 LO PTSPTR1 HI PTSPTR1 LO Ptscon
PTS PWM Remap Mode Control Block
 PWM Tmod
PTS PWM Remap Mode Control Block Register
 18. EPA and PTS Operations for the PWM Remap Mode Example
 Ports
Page
 Bidirectional Ports
I/O Ports Overview
Device I/O Ports
Port Bits Type
 Port Pin Special-function Associated Signals
Bidirectional Port Pins
 Bidirectional Port Control and Status Registers
Bidirectional Port Operation
 8XC196NP, 80C196NU USER’S Manual
 Bidirectional Port Structure
 Sfdir
Logic Table for Bidirectional Ports in I/O Mode
 Bidirectional Port Pin Configurations
 Control Register Values for Each Configuration
Bidirectional Port Pin Configuration Example
Port Configuration Example
 HZ1
Bidirectional Port Considerations
 P2.7/CLKOUT
 Port Pin Extended-address Signal Type
Eport Pins
Design Considerations for External Interrupt Inputs
Eport
 10. Eport Control and Status Registers
Eport Operation
 Eport Block Diagram
 Output Enable
Reset
Complementary Output Mode
Open-drain Output Mode
 Eport Structure
 11. Logic Table for Eport in I/O Mode
Input Mode
12. Logic Table for Eport in Address Mode
Epmode Epdir Epreg
 Configuring Eport Pins for Extended-address Functions
Configuring Eport Pins
Configuring Eport Pins for I/O
13. Configuration Register Settings for Eport Pins
 Eport Status During Instruction Execution
Eport Considerations
 Design Considerations
Page
 Serial I/O SIO Port
Page
 Serial I/O SIO Port Functional Overview
SIO Block Diagram
 Serial Port Signals
Serial I/O Port Signals and Registers
Serial Port Control and Status Registers
Serial
 Sbufrx 1FB8H
P1REG 1FD4H
Sbuftx 1FBAH
Spbaud 1FBCH,1FBDH
 Serial Port Modes
Synchronous Mode Mode
Spstatus 1FB9H
 Asynchronous Modes Modes 1, 2,
Mode 0 Timing
 Mode
Serial Port Frames for Mode
 Mode 2 and 3 Timings
Serial Port Frames in Mode 2
 Programming the Serial Port
Configuring the Serial Port Pins
Programming the Control Register
Programming the Baud Rate and Clock Source
 PAR TB8 PRS REN PEN
Spcon
PAR
 Spcon
 Spbaud
 Baud Rate Spbaud Register Value Note Error Mode Mode 1, 2
Spbaud Values When Using the Internal Clock at 25 MHz
8A2BH
 Enabling the Serial Port Interrupts
Baud Rate Spbaud Register Value † Error Mode
Determining Serial Port Status
8A2CH
 RPE/RB8 TXE
Spstatus
RPE/RB8
 Serial I/O SIO Port
Page
 Pulse-width Modulator
Page
 PWM Functional Overview
PWM Block Diagram 8XC196NP Only
 PWM Signals
PWM Signals and Registers
 PWM Control and Status Registers
PWM Operation
 8XC196NP, 80C196NU USER’S Manual
 Programming the Frequency and Period
Enabled
E6H
FFH
 PWM Output Frequencies 80C196NU
PWM Output Frequencies 8XC196NP
CLK0
CLK1 CLK0
 CONREG0
Programming the Duty Cycle
FEH
CLK1 CLK0
 Clock Prescaler
Disabled
PWM xCONTROL Address
PWM Duty Cycle
 Sample Calculations
PWM Output Alternate Port Function PWM Output Enabled When
Enabling the PWM Outputs
PWM Output Alternate Functions
 D/A Buffer Block Diagram
 Event Processor Array EPA
Page
 EPA Functional Overview
Chapter Event Processor Array EPA
 EPA and Timer/Counter Signals
EPA and TIMER/COUNTER Signals and Registers
Port Pin EPA Signals
EPA
 EPA Control and Status Registers
 TIMER2
TIMER1
 EPA Timer/Counters
TIMER/COUNTER Functional Overview
 Quadrature Clocking Mode
Cascade Mode Timer 2 Only
 Quadrature Mode Interface Quadrature Mode Truth Table
 EPA Channel Functional Overview
Quadrature Mode Timing and Count
 A Single EPA Capture/Compare Channel
Operating in Capture Mode
 EPA Simplified Input-capture Structure
 Action taken when a valid edge occurs
Action Taken when a Valid Edge Occurs
EPA Overruns
EPAxCON.0
 Preventing EPA Overruns
Operating in Compare Mode
Generating a Low-speed PWM Output
 Generating a Medium-speed PWM Output
 Generating a High-speed PWM Output
 Configuring the EPA and Timer/Counter Port Pins
Programming the EPA and TIMER/COUNTERS
Programming the Timers
Generating the Highest-speed PWM Output
 T1CONTROL
Prescaler Divisor Resolution †
Clock Source Direction Source
 T2CONTROL
Prescaler Resolution †
 Mode ROT ON/RT
Example Control Register Settings and EPA Operations
Programming the Capture/Compare Channels
 = 1 = 0
EPA xCON Address Reset State 00H
ROT ON/RT
 Compare Mode Action
Capture Mode Event
 Compare Mode RT
Capture Mode on
ROT
 Determining Event Status
Enabling the EPA Interrupts
Epamask
 Epapend †
12. EPA Interrupt Pending Epapend Register
 Programming Examples for EPA Channels
 EPA Capture Event Program
 Unsigned char Unused Ptscon
EPA PWM Output Program
 10-27
Page
 Minimum Hardware Considerations
Page
 Signal
Minimum Required Signals
Minimum Connections
 Port Where to Find Configuration Information
I/O Port Configuration Guide
Unused Inputs
11.1.2 I/O Port Pin Connections
 Minimum Hardware Connections
 Noise Protection Tips
Applying and Removing Power
 On-chip Oscillator Circuit
ON-CHIP Oscillator Circuitry
 External Crystal Connections
 External Clock Connections
Using AN External Clock Source
 Reset Timing Sequence
Resetting the Device
 Internal Reset Circuitry
Generating an External Reset
 Minimum Reset Circuit
 Issuing an Illegal Idlpd Key Operand
Issuing the Reset RST Instruction
Page
 Special Operating Modes
Page
 Operating Mode Control Signals
Special Operating Mode Signals and Registers
Port Pin Signal Type Description Name
Once
 Port Pin Signal Type Description
Operating Mode Control and Status Registers
PLLEN21
CCR0
 P2DIR 1FD3H
Reducing Power Consumption
P2MODE 1FD1H
P2REG 1FD5H
 Clock Control During Power-saving Modes 8XC196NP
 Clock Control During Power-saving Modes 80C196NU
Idle Mode
 Enabling and Disabling Standby Mode
Standby Mode 80C196NU only
Entering Standby Mode
 Powerdown Mode
Exiting Standby Mode
Enabling and Disabling Powerdown Mode
Entering Powerdown Mode
 Generating a Hardware Reset
Exiting Powerdown Mode
Asserting an External Interrupt Signal
 External RC Circuit
 Selecting C1
 Typical Voltage on the RPD Pin While Exiting Powerdown
 Reserved Test Modes 80C196NU only
Once Mode
 PLLEN2 PLLEN1
C196NU Clock Modes
Page
 Interfacing with External Memory
Page
 Example of Internal and External Addresses
Internal and External Addresses
 External Memory Interface Signals
External Memory Interface Signals
Bit Multiplexed Bus Mode
Bit Demultiplexed Mode
 Description Multiplexed With
Bytes Accessed
ALE
BHE#
 EA#
Name Type Description Multiplexed With
Inst
Ready
 WRL#
CHIP-SELECT Unit
WRH#
 Register Address Description Mnemonic
Chip-select Registers
 Defining Chip-select Address Ranges
Addrcom Address Reset State
Register Address
 Register Address Reset Value
Addrmsk Address Reset State
 Address Mbyte Kbyte Bytes
Base Addresses for Several Sizes of the Address Range
FFB00H FFE00H FFD00H FFF00H
 Controlling Wait States, Bus Width, and Bus Multiplexing
Buscon Address Reset State
WS1 WS0
Wait States
 Chip-select Unit Initial Conditions
BUSCONx Addresses and Reset Values
Initializing the Chip-select Registers
 Example of a Chip-select Setup
 Sram
Chip Contents
Uart
Buscon
 Chip Address Size Number Contents
Chip Configuration Registers and Chip Configuration Bytes
Results for the Chip-select Example
Addrcom Addrmsk
 WS1 WS0 Demux BHE#
CCR0
WS0 WS1
 Remap MODE64
CCR1
Remap
 13-17
 BUS Width and Multiplexing
 Bit Multiplexed Bus
Bit Demultiplexed Bus
 ALE ALE
Bit Demultiplexed Bus
Bit Multiplexed Bus
 13.5.1 a 16-bit Example System
 CS#
13.5.2 16-bit Bus Timings
 Clkout ALE
 13.5.3 8-bit Bus Timings
 A190 Address AD158 High Address
 Wait States Ready Control
Comparison of Multiplexed and Demultiplexed Buses
Bus Description Demultiplexed Bus ns† Multiplexed Bus ns†
 Symbol Definition
11. Ready Signal Timing Definitions
 BHE#, Inst
Ready ALE
 14. Ready Timing Diagram Demultiplexed Mode 8XC196NP
 BUS-HOLD Protocol
15. Ready Timing Diagram Demultiplexed Mode 80C196NU
 12. HOLD#, HLDA# Timing Definitions
Symbol Parameter
 Disabling the Bus-hold Protocol
Enabling the Bus-hold Protocol
Hold Latency
 WRITE-CONTROL Modes
Regaining Bus Control
13. Maximum Hold Latency
Bus Cycle Type
 ALE WR# WRL#
14. Write Signals for Standard and Write Strobe Modes
BHE# WRH#
Bus Word/Byte Standard Write Strobe
 18. Decoding WRL# and WRH#
 RD# WRH# WRL#
System BUS AC Timing Specifications
WE# OE#
 20. Multiplexed System Bus Timing 8XC196NP
 21. Multiplexed System Bus Timing 80C196NU
 22. Demultiplexed System Bus Timing 8XC196NP
 23. Demultiplexed System Bus Timing 80C196NU
Deferred Bus-cycle Mode 80C196NU Only
 24. Deferred Bus-cycle Mode Timing Diagram 80C196NU
 15. AC Timing Symbol Definitions Signals
Explanation of AC Symbols
AC Timing Definitions
Conditions
 Symbol Definition 8XC196Nx Meets These Specifications
 13-44
 13-45
Page
 Instruction Set Reference
Page
 Appendix a Instruction SET Reference
 Opcode
Table A-1. Opcode Map Left Half
 Table A-1. Opcode Map Right Half
 Mnemonic Description
Table A-2. Processor Status Word PSW Flags
Value of Bits Shifted Off
Instruction Quotient Stored Flag Set if Quotient is
 Symbol Description
Table A-4. PSW Flag Setting Symbols
Instruction Jumps to Destination if Continues if
 Variable Description
Table A-5. Operand Variables
 Table A-6. Instruction Set
PSW Flag Settings
Mnemonic Operation
C V VT ST
 Dest ← Dest and SRC
Instruction Format
Andb
 PTRS, Cntreg
 Count ← Count
Mnemonic Operation Instruction Format
Dest
PC ← Dest
 Clear WORD. Clears the value
 Compare BYTES. Subtracts the source
 Dest MOD SRC
 Djnz Decrement and Jump if not Zero
← Dest MOD SRC
 Djnzw Decrement and Jump if not Zero
Dpts Disable Peripheral Transaction
 Count ← Cntreg
Ebmovi Extended Interruptable Block PTRS, Cntreg
Dstptr ← Ptrs + Dstptr ← Srcptr Ptrs ← Srcptr +
EBR
 Onto the stack, then adds to the program
 Epts Enable Peripheral Transaction
 EXT SIGN-EXTEND Integer Into Long
SRC, Dest
 Extb SIGN-EXTEND SHORT-INTEGER Into
 Increment WORD. Increments the value Word operand by
 JGE Jump if Signed Greater than or
 JLE Jump if Signed Less than or Equal
 Negative flag is set, this instruction adds
 JNV Jump if Overflow Flag is Clear
 Jnvt Jump if OVERFLOW-TRAP Flag is
 JVT Jump if OVERFLOW-TRAP Flag is SET
 Mbyte mode
Kbyte mode
 Mulb
MUL
 Mulu
 Mulub
Dest ← Dest PSW Flag Settings
NEG
Negate INTEGER. Negates the value
 Dest ← not Dest
 Dest ← Dest or SRC
 PSW/INTMASK ← SP
INTMASK1/WSR ← SP
 SP ← INTMASK1/WSR INTMASK1 ←
SP ← PSW/INTMASK PSW/INTMASK ←
 Scall
 Wreg,#count
 SHR
 Range of 0 to 31 1FH, inclusive. If
 Shral Arithmetic Right Shift Double
 Skip
Shrl Logical Right Shift DOUBLE-WORD
 SUB
Rightmost operand
 Subc Subtract Words with Borrow DEST, SRC
Subb
Subc
Subcb Subtract Bytes with Borrow DEST, SRC
 Index and #MASK = Offset × Offset + Tbase = Dest PC ← Dest
Tijmp TBASE, INDEX, #MASK
 SRC
 Dest ← Dest XOR SRC
XOR
 Hex Code Instruction Mnemonic
Table A-7. Instruction Opcodes
Clrb Notb Negb
Decb Extb Incb Shrb Shlb Shrab
 Hex Code
 Instruction SET Reference
 8XC196NP, 80C196NU USER’S Manual
 ST Direct
 ELD Indirect
 Arithmetic Group Direct Immediate Indirect Indexed Mnemonic
Table A-8. Instruction Lengths and Hexadecimal Opcodes
Subc Subcb
 Logical Direct Immediate Indirect
 Opcode Length
Stack Direct Immediate Indirect Indexed Mnemonic
POP Popa Popf Push Pusha Pushf
 Extended
Data Direct Immediate
Ebmovi ELD Eldb EST Estb
Direct Immediate
 EBR Ejmp
Jump Direct Immediate
Call Direct Immediate
Lcall RET
 JGE JGT JLE JLT JNC JNE JNH Jnst JNV Jnvt JST JVT
Djnz Djnzw JBC
 Length Opcode
Shift Mnemonic Direct Immediate Indirect Indexed
Special Mnemonic Direct Immediate Indirect
PTS
 Arithmetic Group Indirect
Table A-9. Instruction Execution Times in State Times
Normal Autoinc Short Long Reg Mem
Mem Reg
 DIV Divb Divu Divub
Mnemonic Direct Immed Normal Autoinc Short Long Reg Mem
Logical
 Normal Autoinc Short
Stack Register Indirect
Reg Mem
 Extended-indexed
Data Mnemonic Extended-indirect Normal
Indexed Mnemonic
Autoinc Short Long Reg Mem
 Ljmp Sjmp Tijmp
Mnemonic Direct Immed
 Autoinc Short Long
Indirect Indexed Mnemonic Direct Immed
 Mnemonic Short-Indexed
Conditional Jump
Shift
Mnemonic Direct
 Clrc Clrvt Idlpd
Special Mnemonic Direct Immed Indirect Indexed
NOP RST Setc Skip
Immed Indirect Indexed
Page
 Signal Descriptions
Page
 Table B-1 XC196NP and 80C196NU Signals Arranged by Function
Functional Groupings of Signals
 X8XC196NP
Figure B-1 XC196NP 100-lead Sqfp Package
 Figure B-2 XC196NP 100-lead QFP Package
 X8XC196NU
Figure B-3 C196NU 100-lead Sqfp Package
 Figure B-4 C196NU 100-lead QFP Package
 Table B-3. Signal Descriptions
Signal Descriptions
Table B-2. Description of Columns of Table B-3
Column Heading Description Name
 WRH# BREQ#
Byte High Enable†
 EXTINT30
 VSS
 PLLEN1 PLLEN2
 VSS if either of the following conditions are true
 Asserted only during external memory writes
 Table B-4. Definition of Status Symbols
Default Conditions
RESET# NP/NU
RESET#
 WK1 EPORT.30
Ready WK1 RESET# RPD
ALE WK0
BHE# WK1
 Registers
Page
 Table C-1. Modules and Related Registers
Chip Configuration
CPU EPA
Interrupts
 Table C-2. Register Name, Address, and Reset Status
 EPA2TIME
EPA3CON
EPA3TIME
1FD6H Xxxx P1REG
 WSR1 NU
Xxxx Spbaud
 ACC0x
Table C-3. ACC0x Addresses and Reset Values
ACC0x
 Accstat
 Table C-4. Effect of SME and FME Bit Combinations
 ADDRCOMx
Table C-5. ADDRCOMx Addresses and Reset Values
Addrcom Address
 ADDRMSKx Address Table C-6 Reset State
Table C-6. ADDRMSKx Addresses and Reset Values
ADDRMSKx
 BUSCONx
Table C-7. BUSCONx Addresses and Reset Values
Buscon Address
 CCR0
 CCR1
 CONREG0
 PIN3 PIN2 PIN1 PIN0
Epdir
 Epmode
 XXH
Eppin
 X0H
Epreg
 Epamask
 Epapend
Epapend
 EPA xCON Address
EPAxCON
 EPAxCON Address Table C-8
 Bit Function Number
 Table C-8. EPAxCON Addresses and Reset Values
 EPAxTIME
Table C-9. EPAxTIME Addresses and Reset Values
 Intmask
 FF203EH EXTINT3
INTMASK1
FF203CH EXTINT2
 Intpend
 INTPEND1
 Onesreg
Onesreg
Ffffh
150 One These bits are always equal to Ffffh
 PxDIR
Table C-10. PxDIR Addresses and Reset Values
XDIR Address
PIN7 PIN6 PIN5 PIN4 PIN3 PIN2 PIN1 PIN0
 Table C-12. Special-function Signals for Ports
Table C-11. PxMODE Addresses and Reset Values
PxMODE
 PxPIN
Table C-13. PxPIN Addresses and Reset Values
XPIN Address
Bit Number
 PxREG
Table C-14. PxREG Addresses and Reset Values
PxREG Address Table C-14
P1REG 1FD4H FFH P2REG 1FD5H P3REG 1FDCH P4REG 1FDDH
 PSW
PSW
PSE
 PSW
 Ptssel
 FF200AH EXTINT1
Ptssrv
 PWMxCONTROL
Table C-15. PWMxCONTROL Addresses and Reset Values
 Sbufrx
Sbufrx
Data Received
 Sbuftx
Sbuftx
Data to Transmit
 Xxxxh
 Spbaud
 Baud Rate Spbaud Register Value Note Error Mode
 Spcon
 Spstatus
 T1CONTROL
 T2CONTROL
 Table C-17. TIMERx Addresses and Reset Values
TIMERx
Timer Address
 Byte Windows
WSR
Register Memory 00E0-00FFH
Mnemonic Location
 Register Memory 00E0-00FFH 00C0-00FFH
 TIMER2 †
TIMER1 †
P4DIR 1FDBH 7EH 00FBH 3FH 00DBH 1FH P4MODE 1FD9H
PWM1CONTROL 1FB2H 7DH
 Register Memory 0060-007FH 0040-007FH Mnemonic Location
WSR1
 0060-007FH 0040-007FH Mnemonic Location
 Sbuftx 1FBAH 7DH
PWM0CONTROL 1FB0H 7DH
Spbaud 1FBCH 7DH
Spcon 1FBBH 7DH
 Zeroreg
Zeroreg
150 Zero This register is always equal to zero
Page
 Glossary
Page
 Glossary
 DOUBLE-WORD
 FET
 ISR
 PIC PLL
 PTS
 SFR
 Uart
 Index
Page
 Index
 Index-2
 Index-3
 Index-4
 Index-5
 Index-6
 Index-7
 Index-8
 Index-9
 Index-10
 Index-11
 Index-12