8XC196NP, 80C196NU Microcontroller User’ Manual
 8XC196NP, 80C196NU Microcontroller User’s Manual
 Intel Corporation
 Contents
 Chapter Programming Considerations
 Contents
 Chapter Ports
 Programming the Serial Port
EPA Functional Overview
 8XC196NP, 80C196NU USER’S Manual
 Chapter Interfacing with External Memory
 Appendix C Registers Glossary Index
 Figures
 10-7 Valid EPA Input Events
 13-16
 Tables
 10-5 Example Control Register Settings and EPA Operations
 8XC196NP and 80C196NU Signals Arranged by Function
 Guide to This Manual
Page
 Manual Contents
Chapter Guide to this Manual
 8XC196NP, 80C196NU USER’S Manual
 Notational Conventions and Terminology
Addresses
 Italics
 Units of measure
Related Documents
 Handbooks and Product Information
Application Notes, Application Briefs, and Article Reprints
Title Order Number
 MCS 96 Microcontroller Datasheets Commercial/Express
MCS 96 Microcontroller Datasheets Automotive
 8XC196NP, 80C196NU USER’S Manual
 Intentionally Left Blank
 Intentionally Left Blank
 World Wide Web
Technical Support
Product Literature
Page
 Architectural Overview
Page
 Chapter Architectural Overview
Typical Applications
 Device Features
Block Diagram
Features of the 8XC196NP and 80C196NU
ROM
 CPU Control
Register File
 Register Arithmetic-logic Unit Ralu
Code Execution
 Memory Controller
Instruction Format
 Interrupt Service
Multiply-accumulate 80C196NU Only
 Internal Timing
Clock Circuitry 8XC196NP
 Clock Circuitry 80C196NU
 State Times at Various Frequencies
12.5 MHz
25 MHz
50 MHz
 PLLEN21
Multiplier State Time
 Event Processor Array EPA and Timer/Counters
Internal Peripherals
1 I/O Ports
Serial I/O SIO Port
 Reducing Power Consumption
Pulse-width Modulator PWM
Special Operating Modes
 Testing the Printed Circuit Board
Design Considerations for 80C196NP to 80C196NU Conversions
 8XC196NP, 80C196NU USER’S Manual
 Advanced Math Features
Page
 Chapter Advanced Math Features
Enhanced Multiplication Instructions
 Saturation Mode
Operating Modes
Multiply/Accumulate Example Code
Instructions Execution Time
 Fractional Mode
 Accumulator Register ACC0x
 Accumulator Control and Status Register Accstat
Accstat
Bit Function Number Mnemonic
 Effect of SME and FME Bit Combinations
SME FME
Description
 Programming Considerations
Page
 Overview of the Instruction SET
Operand Type Definitions
Operand Type No. Signed Possible Values Addressing
Restrictions
 BIT Operands
Byte Operands
SHORT-INTEGER Operands
 Word Operands
Integer Operands
DOUBLE-WORD Operands
 LONG-INTEGER Operands
QUAD-WORD Operands
Converting Operands
Conditional Jumps
 Floating Point Operations
Extended Instructions
 EST
Addressing Modes
 Direct Addressing
Immediate Addressing
Indirect Addressing
Definition of Temporary Registers
 Extended Indirect Addressing
Indirect Addressing with Autoincrement
Extended Indirect Addressing with Autoincrement
 Indexed Addressing
Indirect Addressing with the Stack Pointer
Short-indexed Addressing
Long-indexed Addressing
 Extended Indexed Addressing
Zero-indexed Addressing
Extended Zero-indexed Addressing
 Assembly Language Addressing Mode Selections
Extended Addressing
Design Considerations for 1-MBYTE Devices
Software Standards and Conventions
 Using Registers
Addressing 32-bit Operands
Addressing 64-bit Operands
 Linking Subroutines
 Software Protection Features and Guidelines
 Memory Partitions
Page
 Chapter Memory Partitions
Memory MAP Overview
 FFH 2FH 1FH 0FH F1H
F0H
 Memory Partitions
FFH
80C196NP/NU External 83C196NP ROM
 XC196NP and 80C196NU Memory Map
Hex Description Addressing Modes
 Program Memory Access for the 83C196NP
External Memory
Program and Special-purpose Memory
Program Memory in Page FFH
 Special-purpose Memory Access for the 83C196NP
Special-purpose Memory
XC196NP and 80C196NU Special-purpose Memory Addresses
 Chip Configuration Bytes
Peripheral Special-function Registers SFRs
Reserved Memory Locations
Interrupt and PTS Vectors
 Peripheral SFRs
 1F7EH
1F7CH
1F7AH
1F4EH
 Stack Pointer
CPU SFRs
 Register File Memory Addresses
General-purpose Register RAM
Stack Pointer SP
Address Description Addressing Modes Range
 CPU Special-function Registers SFRs
CPU SFRs
8XC196NP CPU SFRs Address High Odd Byte Low Even Byte
80C196NU CPU SFRs Address High Odd Byte Low Even Byte
 Windowing
8XC196NP
 Selecting a Window
WSR
Hlden
Bit Function
 Selecting a Window of the Upper Register File
 Addressing a Location Through a Window
 10. Windows
Base WSR or WSR1 Value WSR Value for
Peripheral SFRs
Upper Register File
 11. Windowed Base Addresses
2.1 32-byte Windowing Example
2.2 64-byte Windowing Example
2.3 128-byte Windowing Example
 Using the Linker Locator to Set Up a Window
Unsupported Locations Windowing Example 8XC196NP Only
 Type Base Length Alignment
 This listing shows the disassembled code
Windowing and Addressing Modes
 Remapping Internal ROM 83C196NP only
 Accessing Data
Fetching Code and Data in the 1-MBYTE and 64-KBYTE Modes
Fetching Instructions
Epcpc
 Formation of Extended and Nonextended Addresses
 Code Fetches in the 1-Mbyte Mode
Code Fetches in the 64-Kbyte Mode
 Data Fetches in the 1-Mbyte and 64-Kbyte Modes
80C196NP and 80C196NU
 Memory Configuration Examples
Example 1 Using the 64-Kbyte Mode
RD# WR#
CE#
 12. Memory Map for the System in Figure
Address Description
80C196NP and 80C196NU External flash memory
80C196NP and 80C196NU Unimplemented
 Example 2 a 64-Kbyte System with Additional Data Storage
RD# WR# CE#
Ffffffh D70 OE# WE#
02FFFFH
 13. Memory Map for the System in Figure
80C196NP and 80C196NU External RAM
 Example 3 Using 1-Mbyte Mode
01FFFFH
OE# WE# OE# WRH# WRL# RD#
 14. Memory Map for the System in Figure
80C196NP and 80C196NU External memory
Fbffffh
 Standard and PTS Interrupts
Page
 Chapter Standard and PTS Interrupts
Overview of Interrupts
 Flow Diagram for PTS and Standard Interrupts
 Interrupt Signals and Registers
Interrupt Signals
Interrupt and PTS Control and Status Registers
 Interrupt Sources and Priorities
Special Interrupts
Intpend
Ptssel
 Interrupt Controller PTS Service
Interrupt Sources, Vectors, and Priorities
Unimplemented Opcode
Software Trap
 External Interrupt Pins
Multiplexed Interrupt Sources
End-of-PTS Interrupts
1.3 NMI
 Interrupt Latency
Situations that Increase Interrupt Latency
 Calculating Latency
Standard Interrupt Latency
 Standard Interrupt Response Time PTS Interrupt Latency
 PTS Mode Execution Time in State Times
Programming the Interrupts
Execution Times for PTS Cycles
 Programming Considerations for Multiplexed Interrupts
Ptssel
Bit Mnemonic Interrupt PTS Vector
 Intmask
EPA0 EXTINT1 EXTINT0 OVRTM2 OVRTM1
Bit Mnemonic Interrupt Standard Vector
 Modifying Interrupt Priorities
INTMASK1
NMI EXTINT3 EXTINT2
EPA3 EPA2 EPA1
 RET Cseg AT 0FF200CH
 Determining the Source of an Interrupt
 Interrupt Pending Intpend Register
Intpend
 Initializing the PTS Control Blocks
INTPEND1
 PWM Toggle Mode
PWM Remap Mode
Specifying the PTS Count
Single Transfer
 Selecting the PTS Mode
Ptssrv
EPA3 EPA2 EPA1 EXTINT0 OVRTM1 OVRTM2
 Single Transfer Mode
Ptscon
Address Ptspcb +
 PTS Single Transfer Mode Control Block
Ptsdst HI Ptsdst LO Ptssrc HI Ptssrc LO Ptscon Ptscount
Register Location Function
Ptsdst Ptscb +
 8XC196NP, 80C196NU USER’S Manual
 Block Transfer Mode
Single Transfer Mode Ptscb
Block Transfer Mode Ptscb
Ptscount = 09H
 PTS Block Transfer Mode Control Block
Ptsblock Ptscb +
 Increment the contents of Ptssrc after each byte or word
 PWM Toggle Mode PWM Remap Mode
PWM Modes
Comparison of PWM Modes
PTSCONST2
 PWM Toggle Mode Example
14. a Generic PWM Waveform
 PWM Toggle Mode Ptscb
PTSCONST1 HI = T1 HI PTSCONST1 LO = T1 LO PTSPTR1 HI = 1FH
 PTSCONST2 H
PTSCONST2 L
PTSCONST1 H
PTSCONST1 L
 Ptscon Ptscb +
Tmod
 16. EPA and PTS Operations for the PWM Toggle Mode Example
 PWM Remap Mode Example
 PWM Remap Mode Ptscb
 PTS PWM Remap Mode Control Block
PTSCONST1 HI PTSCONST1 LO PTSPTR1 HI PTSPTR1 LO Ptscon
 PTS PWM Remap Mode Control Block Register
PWM Tmod
 18. EPA and PTS Operations for the PWM Remap Mode Example
 Ports
Page
 I/O Ports Overview
Bidirectional Ports
Device I/O Ports
Port Bits Type
 Bidirectional Port Pins
Port Pin Special-function Associated Signals
 Bidirectional Port Operation
Bidirectional Port Control and Status Registers
 8XC196NP, 80C196NU USER’S Manual
 Bidirectional Port Structure
 Logic Table for Bidirectional Ports in I/O Mode
Sfdir
 Bidirectional Port Pin Configurations
 Bidirectional Port Pin Configuration Example
Control Register Values for Each Configuration
Port Configuration Example
 Bidirectional Port Considerations
HZ1
 P2.7/CLKOUT
 Eport Pins
Port Pin Extended-address Signal Type
Design Considerations for External Interrupt Inputs
Eport
 Eport Operation
10. Eport Control and Status Registers
 Eport Block Diagram
 Reset
Output Enable
Complementary Output Mode
Open-drain Output Mode
 Eport Structure
 Input Mode
11. Logic Table for Eport in I/O Mode
12. Logic Table for Eport in Address Mode
Epmode Epdir Epreg
 Configuring Eport Pins
Configuring Eport Pins for Extended-address Functions
Configuring Eport Pins for I/O
13. Configuration Register Settings for Eport Pins
 Eport Considerations
Eport Status During Instruction Execution
 Design Considerations
Page
 Serial I/O SIO Port
Page
 SIO Block Diagram
Serial I/O SIO Port Functional Overview
 Serial I/O Port Signals and Registers
Serial Port Signals
Serial Port Control and Status Registers
Serial
 P1REG 1FD4H
Sbufrx 1FB8H
Sbuftx 1FBAH
Spbaud 1FBCH,1FBDH
 Synchronous Mode Mode
Serial Port Modes
Spstatus 1FB9H
 Mode 0 Timing
Asynchronous Modes Modes 1, 2,
 Serial Port Frames for Mode
Mode
 Serial Port Frames in Mode 2
Mode 2 and 3 Timings
 Configuring the Serial Port Pins
Programming the Serial Port
Programming the Control Register
Programming the Baud Rate and Clock Source
 Spcon
PAR TB8 PRS REN PEN
PAR
 Spcon
 Spbaud
 Spbaud Values When Using the Internal Clock at 25 MHz
Baud Rate Spbaud Register Value Note Error Mode Mode 1, 2
8A2BH
 Baud Rate Spbaud Register Value † Error Mode
Enabling the Serial Port Interrupts
Determining Serial Port Status
8A2CH
 Spstatus
RPE/RB8 TXE
RPE/RB8
 Serial I/O SIO Port
Page
 Pulse-width Modulator
Page
 PWM Block Diagram 8XC196NP Only
PWM Functional Overview
 PWM Signals and Registers
PWM Signals
 PWM Operation
PWM Control and Status Registers
 8XC196NP, 80C196NU USER’S Manual
 Enabled
Programming the Frequency and Period
E6H
FFH
 PWM Output Frequencies 8XC196NP
PWM Output Frequencies 80C196NU
CLK0
CLK1 CLK0
 Programming the Duty Cycle
CONREG0
FEH
CLK1 CLK0
 Disabled
Clock Prescaler
PWM xCONTROL Address
PWM Duty Cycle
 PWM Output Alternate Port Function PWM Output Enabled When
Sample Calculations
Enabling the PWM Outputs
PWM Output Alternate Functions
 D/A Buffer Block Diagram
 Event Processor Array EPA
Page
 Chapter Event Processor Array EPA
EPA Functional Overview
 EPA and TIMER/COUNTER Signals and Registers
EPA and Timer/Counter Signals
Port Pin EPA Signals
EPA
 EPA Control and Status Registers
 TIMER1
TIMER2
 TIMER/COUNTER Functional Overview
EPA Timer/Counters
 Cascade Mode Timer 2 Only
Quadrature Clocking Mode
 Quadrature Mode Interface Quadrature Mode Truth Table
 Quadrature Mode Timing and Count
EPA Channel Functional Overview
 Operating in Capture Mode
A Single EPA Capture/Compare Channel
 EPA Simplified Input-capture Structure
 Action Taken when a Valid Edge Occurs
Action taken when a valid edge occurs
EPA Overruns
EPAxCON.0
 Operating in Compare Mode
Preventing EPA Overruns
Generating a Low-speed PWM Output
 Generating a Medium-speed PWM Output
 Generating a High-speed PWM Output
 Programming the EPA and TIMER/COUNTERS
Configuring the EPA and Timer/Counter Port Pins
Programming the Timers
Generating the Highest-speed PWM Output
 Prescaler Divisor Resolution †
T1CONTROL
Clock Source Direction Source
 Prescaler Resolution †
T2CONTROL
 Example Control Register Settings and EPA Operations
Mode ROT ON/RT
Programming the Capture/Compare Channels
 EPA xCON Address Reset State 00H
= 1 = 0
ROT ON/RT
 Capture Mode Event
Compare Mode Action
 Capture Mode on
Compare Mode RT
ROT
 Enabling the EPA Interrupts
Determining Event Status
Epamask
 12. EPA Interrupt Pending Epapend Register
Epapend †
 Programming Examples for EPA Channels
 EPA Capture Event Program
 EPA PWM Output Program
Unsigned char Unused Ptscon
 10-27
Page
 Minimum Hardware Considerations
Page
 Minimum Required Signals
Signal
Minimum Connections
 I/O Port Configuration Guide
Port Where to Find Configuration Information
Unused Inputs
11.1.2 I/O Port Pin Connections
 Minimum Hardware Connections
 Applying and Removing Power
Noise Protection Tips
 ON-CHIP Oscillator Circuitry
On-chip Oscillator Circuit
 External Crystal Connections
 Using AN External Clock Source
External Clock Connections
 Resetting the Device
Reset Timing Sequence
 Generating an External Reset
Internal Reset Circuitry
 Minimum Reset Circuit
 Issuing the Reset RST Instruction
Issuing an Illegal Idlpd Key Operand
Page
 Special Operating Modes
Page
 Special Operating Mode Signals and Registers
Operating Mode Control Signals
Port Pin Signal Type Description Name
Once
 Operating Mode Control and Status Registers
Port Pin Signal Type Description
PLLEN21
CCR0
 Reducing Power Consumption
P2DIR 1FD3H
P2MODE 1FD1H
P2REG 1FD5H
 Clock Control During Power-saving Modes 8XC196NP
 Idle Mode
Clock Control During Power-saving Modes 80C196NU
 Standby Mode 80C196NU only
Enabling and Disabling Standby Mode
Entering Standby Mode
 Exiting Standby Mode
Powerdown Mode
Enabling and Disabling Powerdown Mode
Entering Powerdown Mode
 Exiting Powerdown Mode
Generating a Hardware Reset
Asserting an External Interrupt Signal
 External RC Circuit
 Selecting C1
 Typical Voltage on the RPD Pin While Exiting Powerdown
 Once Mode
Reserved Test Modes 80C196NU only
 C196NU Clock Modes
PLLEN2 PLLEN1
Page
 Interfacing with External Memory
Page
 Internal and External Addresses
Example of Internal and External Addresses
 External Memory Interface Signals
External Memory Interface Signals
Bit Multiplexed Bus Mode
Bit Demultiplexed Mode
 Bytes Accessed
Description Multiplexed With
ALE
BHE#
 Name Type Description Multiplexed With
EA#
Inst
Ready
 CHIP-SELECT Unit
WRL#
WRH#
 Chip-select Registers
Register Address Description Mnemonic
 Addrcom Address Reset State
Defining Chip-select Address Ranges
Register Address
 Addrmsk Address Reset State
Register Address Reset Value
 Base Addresses for Several Sizes of the Address Range
Address Mbyte Kbyte Bytes
FFB00H FFE00H FFD00H FFF00H
 Buscon Address Reset State
Controlling Wait States, Bus Width, and Bus Multiplexing
WS1 WS0
Wait States
 BUSCONx Addresses and Reset Values
Chip-select Unit Initial Conditions
Initializing the Chip-select Registers
 Example of a Chip-select Setup
 Chip Contents
Sram
Uart
Buscon
 Chip Configuration Registers and Chip Configuration Bytes
Chip Address Size Number Contents
Results for the Chip-select Example
Addrcom Addrmsk
 CCR0
WS1 WS0 Demux BHE#
WS0 WS1
 CCR1
Remap MODE64
Remap
 13-17
 BUS Width and Multiplexing
 Bit Demultiplexed Bus
Bit Multiplexed Bus
 Bit Demultiplexed Bus
ALE ALE
Bit Multiplexed Bus
 13.5.1 a 16-bit Example System
 13.5.2 16-bit Bus Timings
CS#
 Clkout ALE
 13.5.3 8-bit Bus Timings
 A190 Address AD158 High Address
 Comparison of Multiplexed and Demultiplexed Buses
Wait States Ready Control
Bus Description Demultiplexed Bus ns† Multiplexed Bus ns†
 11. Ready Signal Timing Definitions
Symbol Definition
 Ready ALE
BHE#, Inst
 14. Ready Timing Diagram Demultiplexed Mode 8XC196NP
 15. Ready Timing Diagram Demultiplexed Mode 80C196NU
BUS-HOLD Protocol
 Symbol Parameter
12. HOLD#, HLDA# Timing Definitions
 Enabling the Bus-hold Protocol
Disabling the Bus-hold Protocol
Hold Latency
 Regaining Bus Control
WRITE-CONTROL Modes
13. Maximum Hold Latency
Bus Cycle Type
 14. Write Signals for Standard and Write Strobe Modes
ALE WR# WRL#
BHE# WRH#
Bus Word/Byte Standard Write Strobe
 18. Decoding WRL# and WRH#
 System BUS AC Timing Specifications
RD# WRH# WRL#
WE# OE#
 20. Multiplexed System Bus Timing 8XC196NP
 21. Multiplexed System Bus Timing 80C196NU
 22. Demultiplexed System Bus Timing 8XC196NP
 Deferred Bus-cycle Mode 80C196NU Only
23. Demultiplexed System Bus Timing 80C196NU
 24. Deferred Bus-cycle Mode Timing Diagram 80C196NU
 Explanation of AC Symbols
15. AC Timing Symbol Definitions Signals
AC Timing Definitions
Conditions
 Symbol Definition 8XC196Nx Meets These Specifications
 13-44
 13-45
Page
 Instruction Set Reference
Page
 Appendix a Instruction SET Reference
 Table A-1. Opcode Map Left Half
Opcode
 Table A-1. Opcode Map Right Half
 Table A-2. Processor Status Word PSW Flags
Mnemonic Description
Value of Bits Shifted Off
Instruction Quotient Stored Flag Set if Quotient is
 Table A-4. PSW Flag Setting Symbols
Symbol Description
Instruction Jumps to Destination if Continues if
 Table A-5. Operand Variables
Variable Description
 PSW Flag Settings
Table A-6. Instruction Set
Mnemonic Operation
C V VT ST
 Instruction Format
Dest ← Dest and SRC
Andb
 PTRS, Cntreg
 Mnemonic Operation Instruction Format
Count ← Count
Dest
PC ← Dest
 Clear WORD. Clears the value
 Compare BYTES. Subtracts the source
 Dest MOD SRC
 ← Dest MOD SRC
Djnz Decrement and Jump if not Zero
 Dpts Disable Peripheral Transaction
Djnzw Decrement and Jump if not Zero
 Ebmovi Extended Interruptable Block PTRS, Cntreg
Count ← Cntreg
Dstptr ← Ptrs + Dstptr ← Srcptr Ptrs ← Srcptr +
EBR
 Onto the stack, then adds to the program
 Epts Enable Peripheral Transaction
 SRC, Dest
EXT SIGN-EXTEND Integer Into Long
 Extb SIGN-EXTEND SHORT-INTEGER Into
 Increment WORD. Increments the value Word operand by
 JGE Jump if Signed Greater than or
 JLE Jump if Signed Less than or Equal
 Negative flag is set, this instruction adds
 JNV Jump if Overflow Flag is Clear
 Jnvt Jump if OVERFLOW-TRAP Flag is
 JVT Jump if OVERFLOW-TRAP Flag is SET
 Kbyte mode
Mbyte mode
 MUL
Mulb
 Mulu
 Dest ← Dest PSW Flag Settings
Mulub
NEG
Negate INTEGER. Negates the value
 Dest ← not Dest
 Dest ← Dest or SRC
 INTMASK1/WSR ← SP
PSW/INTMASK ← SP
 SP ← PSW/INTMASK PSW/INTMASK ←
SP ← INTMASK1/WSR INTMASK1 ←
 Scall
 Wreg,#count
 SHR
 Range of 0 to 31 1FH, inclusive. If
 Shral Arithmetic Right Shift Double
 Shrl Logical Right Shift DOUBLE-WORD
Skip
 Rightmost operand
SUB
 Subb
Subc Subtract Words with Borrow DEST, SRC
Subc
Subcb Subtract Bytes with Borrow DEST, SRC
 Tijmp TBASE, INDEX, #MASK
Index and #MASK = Offset × Offset + Tbase = Dest PC ← Dest
 SRC
 XOR
Dest ← Dest XOR SRC
 Table A-7. Instruction Opcodes
Hex Code Instruction Mnemonic
Clrb Notb Negb
Decb Extb Incb Shrb Shlb Shrab
 Hex Code
 Instruction SET Reference
 8XC196NP, 80C196NU USER’S Manual
 ST Direct
 ELD Indirect
 Table A-8. Instruction Lengths and Hexadecimal Opcodes
Arithmetic Group Direct Immediate Indirect Indexed Mnemonic
Subc Subcb
 Logical Direct Immediate Indirect
 Stack Direct Immediate Indirect Indexed Mnemonic
Opcode Length
POP Popa Popf Push Pusha Pushf
 Data Direct Immediate
Extended
Ebmovi ELD Eldb EST Estb
Direct Immediate
 Jump Direct Immediate
EBR Ejmp
Call Direct Immediate
Lcall RET
 Djnz Djnzw JBC
JGE JGT JLE JLT JNC JNE JNH Jnst JNV Jnvt JST JVT
 Shift Mnemonic Direct Immediate Indirect Indexed
Length Opcode
Special Mnemonic Direct Immediate Indirect
PTS
 Table A-9. Instruction Execution Times in State Times
Arithmetic Group Indirect
Normal Autoinc Short Long Reg Mem
Mem Reg
 Mnemonic Direct Immed Normal Autoinc Short Long Reg Mem
DIV Divb Divu Divub
Logical
 Stack Register Indirect
Normal Autoinc Short
Reg Mem
 Data Mnemonic Extended-indirect Normal
Extended-indexed
Indexed Mnemonic
Autoinc Short Long Reg Mem
 Mnemonic Direct Immed
Ljmp Sjmp Tijmp
 Indirect Indexed Mnemonic Direct Immed
Autoinc Short Long
 Conditional Jump
Mnemonic Short-Indexed
Shift
Mnemonic Direct
 Special Mnemonic Direct Immed Indirect Indexed
Clrc Clrvt Idlpd
NOP RST Setc Skip
Immed Indirect Indexed
Page
 Signal Descriptions
Page
 Functional Groupings of Signals
Table B-1 XC196NP and 80C196NU Signals Arranged by Function
 Figure B-1 XC196NP 100-lead Sqfp Package
X8XC196NP
 Figure B-2 XC196NP 100-lead QFP Package
 Figure B-3 C196NU 100-lead Sqfp Package
X8XC196NU
 Figure B-4 C196NU 100-lead QFP Package
 Signal Descriptions
Table B-3. Signal Descriptions
Table B-2. Description of Columns of Table B-3
Column Heading Description Name
 Byte High Enable†
WRH# BREQ#
 EXTINT30
 VSS
 PLLEN1 PLLEN2
 VSS if either of the following conditions are true
 Asserted only during external memory writes
 Default Conditions
Table B-4. Definition of Status Symbols
RESET# NP/NU
RESET#
 Ready WK1 RESET# RPD
WK1 EPORT.30
ALE WK0
BHE# WK1
 Registers
Page
 Chip Configuration
Table C-1. Modules and Related Registers
CPU EPA
Interrupts
 Table C-2. Register Name, Address, and Reset Status
 EPA3CON
EPA2TIME
EPA3TIME
1FD6H Xxxx P1REG
 Xxxx Spbaud
WSR1 NU
 Table C-3. ACC0x Addresses and Reset Values
ACC0x
ACC0x
 Accstat
 Table C-4. Effect of SME and FME Bit Combinations
 Table C-5. ADDRCOMx Addresses and Reset Values
ADDRCOMx
Addrcom Address
 Table C-6. ADDRMSKx Addresses and Reset Values
ADDRMSKx Address Table C-6 Reset State
ADDRMSKx
 Table C-7. BUSCONx Addresses and Reset Values
BUSCONx
Buscon Address
 CCR0
 CCR1
 CONREG0
 Epdir
PIN3 PIN2 PIN1 PIN0
 Epmode
 Eppin
XXH
 Epreg
X0H
 Epamask
 Epapend
Epapend
 EPAxCON
EPA xCON Address
 EPAxCON Address Table C-8
 Bit Function Number
 Table C-8. EPAxCON Addresses and Reset Values
 Table C-9. EPAxTIME Addresses and Reset Values
EPAxTIME
 Intmask
 INTMASK1
FF203EH EXTINT3
FF203CH EXTINT2
 Intpend
 INTPEND1
 Onesreg
Onesreg
Ffffh
150 One These bits are always equal to Ffffh
 Table C-10. PxDIR Addresses and Reset Values
PxDIR
XDIR Address
PIN7 PIN6 PIN5 PIN4 PIN3 PIN2 PIN1 PIN0
 Table C-11. PxMODE Addresses and Reset Values
Table C-12. Special-function Signals for Ports
PxMODE
 Table C-13. PxPIN Addresses and Reset Values
PxPIN
XPIN Address
Bit Number
 Table C-14. PxREG Addresses and Reset Values
PxREG
PxREG Address Table C-14
P1REG 1FD4H FFH P2REG 1FD5H P3REG 1FDCH P4REG 1FDDH
 PSW
PSW
PSE
 PSW
 Ptssel
 Ptssrv
FF200AH EXTINT1
 Table C-15. PWMxCONTROL Addresses and Reset Values
PWMxCONTROL
 Sbufrx
Sbufrx
Data Received
 Sbuftx
Sbuftx
Data to Transmit
 Xxxxh
 Spbaud
 Baud Rate Spbaud Register Value Note Error Mode
 Spcon
 Spstatus
 T1CONTROL
 T2CONTROL
 TIMERx
Table C-17. TIMERx Addresses and Reset Values
Timer Address
 WSR
Byte Windows
Register Memory 00E0-00FFH
Mnemonic Location
 Register Memory 00E0-00FFH 00C0-00FFH
 TIMER1 †
TIMER2 †
P4DIR 1FDBH 7EH 00FBH 3FH 00DBH 1FH P4MODE 1FD9H
PWM1CONTROL 1FB2H 7DH
 WSR1
Register Memory 0060-007FH 0040-007FH Mnemonic Location
 0060-007FH 0040-007FH Mnemonic Location
 PWM0CONTROL 1FB0H 7DH
Sbuftx 1FBAH 7DH
Spbaud 1FBCH 7DH
Spcon 1FBBH 7DH
 Zeroreg
Zeroreg
150 Zero This register is always equal to zero
Page
 Glossary
Page
 Glossary
 DOUBLE-WORD
 FET
 ISR
 PIC PLL
 PTS
 SFR
 Uart
 Index
Page
 Index
 Index-2
 Index-3
 Index-4
 Index-5
 Index-6
 Index-7
 Index-8
 Index-9
 Index-10
 Index-11
 Index-12