Intel 8XC196NP, 80C196NU, Microcontroller manual Spstatus

		REGISTERS
		SP_STATUS
SP_STATUS	Address:	1FB9H
	Reset State:	0BH

The serial port status (SP_STATUS) register contains bits that indicate the status of the serial port.

7

RPE/RB8 RI TI FE

0

TXE OE — —

Bit	Bit	Function
Number	Mnemonic
7	RPE/RB8	Received Parity Error/Received Bit 8
		RPE is set if parity is disabled (SP_CON.2 = 0) and the ninth data bit
		received is high.
		RB8 is set if parity is enabled (SP_CON.2 = 1) and a parity error
		occurred.
		Reading SP_STATUS clears this bit.
6	RI	Receive Interrupt
		This bit is set when the last data bit is sampled. Reading SP_STATUS
		clears this bit.
		This bit need not be clear for the serial port to receive data.
5	TI	Transmit Interrupt
		This bit is set at the beginning of the stop bit transmission. Reading
		SP_STATUS clears this bit.
4	FE	Framing Error
		This bit is set if a stop bit is not found within the appropriate period of
		time. Reading SP_STATUS clears this bit.
3	TXE	SBUF_TX Empty
		This bit is set if the transmit buffer is empty and ready to accept up to two
		bytes. It is cleared when a byte is written to SBUF_TX.
2	OE	Overrun Error
		This bit is set if data in the receive shift register is loaded into SBUF_RX
		before the previous bit is read. Reading SP_STATUS clears this bit.
1:0	—	Reserved. These bits are undefined.

C-45