INSTRUCTION SET REFERENCE

Table A-6. Instruction Set (Continued)

Mnemonic

 

 

 

Operation

 

 

 

 

Instruction Format

ANDB

LOGICAL AND BYTES. ANDs the two source

 

DEST, SRC1, SRC2

(3 operands)

byte operands and stores the result into the

ANDB

Dbreg, Sbreg, baop

 

destination operand. The result has ones in

 

(010100aa) (baop) (Sbreg) (Dbreg)

 

only the bit positions in which both operands

 

 

 

 

had a “1” and zeros in all other bit positions.

 

 

 

(DEST) ← (SRC1) AND (SRC2)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PSW Flag Settings

 

 

 

 

 

 

Z

N

C

V

VT

ST

 

 

 

 

 

✓

✓

0

0

—

—

 

 

 

 

 

 

 

BMOV

BLOCK MOVE. Moves a block of word data

 

PTRS, CNTREG

 

from one location in memory to another. The

BMOV

lreg, wreg

 

source and destination addresses are

 

(11000001) (wreg) (lreg)

 

calculated using the indirect with autoin-

 

 

 

 

crement addressing mode. A long register

 

 

 

(PTRS) addresses the source and destination

NOTE: The pointers are autoincre-

 

pointers, which are stored in adjacent word

 

 

mented during this instruction.

 

registers. The source pointer (SRCPTR) is

 

 

 

However, CNTREG is not decre-

 

the low word and the destination pointer

 

 

 

mented. Therefore, it is easy to

 

(DSTPTR) is the high word of PTRS. A word

 

 

 

unintentionally create a long,

 

register (CNTREG) specifies the number of

 

 

 

uninterruptible operation with the

 

transfers. The blocks of data can be located

 

 

 

BMOV instruction. Use the

 

anywhere in page 00H of register RAM, but

 

 

 

BMOVI instruction for an interrupt-

 

should not overlap. Because the source

 

 

 

ible operation.

 

(SRCPTR) and destination (DSTPTR)

 

 

 

 

 

pointers are 16 bits wide, this instruction uses

 

 

 

nonextended data moves. It cannot operate

 

 

 

across page boundaries. For example,

 

 

 

SRCPTR cannot point to a location on page

 

 

 

05 while DSTPTR points to page 00.

 

 

 

SRCPTR and DSTPTR will operate from the

 

 

 

page defined by EP_REG. EP_REG should

 

 

 

be set to 00H to select page 00H (see

 

 

 

“Accessing Data” on page 5-23). (The

 

 

 

80C196NU forces EP_REG to 00H.)

 

 

COUNT ← (CNTREG) LOOP: SRCPTR ← (PTRS) DSTPTR ← (PTRS + 2) (DSTPTR) ← (SRCPTR) (PTRS) ← SRCPTR + 2 (PTRS + 2) ← DSTPTR + 2 COUNT ← COUNT – 1

if COUNT ≠ 0 then go to LOOP

PSW Flag Settings

Z

 

N

 

C

V

VT

ST

—

—

 

—

—

—

—

 

A-9

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Intel Microcontroller, 80C196NU, 8XC196NP manual Bmov, PTRS, Cntreg
Page 313 Page 315

Microcontroller, 80C196NU, 8XC196NP specifications

The Intel 8XC196NP and 80C196NU microcontrollers are part of Intel's renowned 16-bit microcontroller series that gained popularity in the 1980s and 1990s for embedded systems applications. Designed for a variety of applications, these microcontrollers are characterized by their robust performance, versatility, and industry-standard architecture.

The 8XC196NP features an enhanced instruction set with over 100 instructions, allowing for efficient code execution. It operates at clock speeds up to 16 MHz, which contributes to improved performance in time-sensitive applications. The microcontroller is equipped with a 16-bit data bus, enabling more efficient data handling compared to its 8-bit predecessors, thus accommodating complex algorithms and large data sets.

In terms of memory architecture, the 8XC196NP supports an addressable memory space of up to 64 KB of program memory and 64 KB of data memory. This configuration provides sufficient space for large applications while ensuring fast data access. The microcontroller includes integrated features such as timers, serial I/O capabilities, and interrupt processing, which enhance its functionality for real-time applications and control mechanisms.

The 80C196NU, on the other hand, is designed for lower power operation, making it suitable for battery-powered devices. This microcontroller maintains similar features to the 8XC196NP while offering advancements that support low-power consumption. The 80C196NU can also function in a range of temperature environments, making it adaptable for industrial applications.

Both the 8XC196NP and 80C196NU support external memory interfacing, allowing designers to expand the system's capability by connecting additional ROM and RAM. This flexibility makes them appealing for developing complex systems, such as motor controls, industrial automation, and consumer electronics.

Another standout feature of these microcontrollers is their built-in debugging capabilities. Intel provided hardware and software tools that enabled developers to test and troubleshoot their applications effectively, reducing the development time and increasing reliability.

Overall, the Intel 8XC196NP and 80C196NU microcontrollers stand out for their dependability, versatility, and performance, contributing significantly to the evolution of embedded system design. Their legacy continues to influence modern microcontroller technology, ensuring their relevance in a wide array of applications today.
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