Intel 8XC196NP, 80C196NU manual Reducing Power Consumption, P2DIR 1FD3H, P2MODE 1FD1H, P2REG 1FD5H

SPECIAL OPERATING MODES

Table 12-2. Operating Mode Control and Status Registers (Continued)

Mnemonic	Address	Description
INT_MASK1	0013H	Interrupt Mask 1
		Bits 5 and 6 of this register enable and disable (mask) the
		external interrupts, EXTINT2 and EXTINT3.
INT_PEND	0009H	Interrupt Pending
		Bits 3 and 4 of this register are set to indicate a pending external
		interrupt, EXTINT0 and EXTINT1.
INT_PEND1	0012H	Interrupt Pending 1
		Bits 5 and 6 of this register are set to indicate a pending external
		interrupt, EXTINT2 and EXTINT3.
P2_DIR	1FD3H	Port x Direction
P3_DIR	1FDAH	Each bit of Px_DIR controls the direction of the corresponding pin.
		Clearing a bit configures a pin as a complementary output; setting
		a bit configures a pin as an input or open-drain output. (Open-
		drain outputs require external pull-ups.)
P2_MODE	1FD1H	Port x Mode
P3_MODE	1FD8H	Each bit of Px_MODE controls whether the corresponding pin
		functions as a standard I/O port pin or as a special-function
		signal. Setting a bit configures a pin as a special-function signal;
		clearing a bit configures a pin as a standard I/O port pin.
P2_REG	1FD5H	Port x Data Output
P3_REG	1FDCH	For an input, set the corresponding Px_REG bit.
		For an output, write the data to be driven out by each pin to the
		corresponding bit of Px_REG. When a pin is configured as
		standard I/O (Px_MODE.y = 0), the result of a CPU write to
		Px_REG is immediately visible on the pin. When a pin is
		configured as a special-function signal (Px_MODE.y = 1), the
		associated on-chip peripheral or off-chip component controls the
		pin. The CPU can still write to Px_REG, but the pin is unaffected
		until it is switched back to its standard I/O function.
		This feature allows software to configure a pin as standard I/O
		(clear Px_MODE.y), initialize or overwrite the pin value, then
		configure the pin as a special-function signal (set Px_MODE.y). In
		this way, initialization, fault recovery, exception handling, etc., can
		be done without changing the operation of the associated
		peripheral.

12.2 REDUCING POWER CONSUMPTION

Each power-saving mode conserves power by disabling portions of the internal clock circuitry (Figure 12-1 and Figure 12-2). The following paragraphs describe each mode in detail.

12-3