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Intel 8XC196NP, Microcontroller manual Multiplexed System Bus Timing 80C196NU

Models: Microcontroller 80C196NU 8XC196NP

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8XC196NP, 80C196NU USER’S MANUAL
	TCLCL
	T	TCHDV
	TCLLH	TRLCL	TCHCL
CLKOUT
	TLLCH		TRHLH
		TLHLH		TLHLL
		T		TLHLL
		LLRL
ALE
		TRLRH	TRHDZ
		TRLAZ	TRHDZ
RD#
		TRLDV
	TLLAX
	TAVLL	TAVDV
AD15:0		TAVDV
AD15:0	Address Out	Data In
(read)	Address Out	Data In
(read)
			TCHWH
	TLLWL		TWHLH
		TWLWH	TWHQX
WR#
		TQVWH
AD15:0	Address Out		Data Out	Address Out
(write)	Address Out		Data Out	Address Out
(write)
			TWHBX, TRHBX
BHE#, INST
			TWHAX,TRHAX
AD15:8
			TWHSH,TRHSH
A19:16
CSx#
				T0011-02

Figure 13-21. Multiplexed System Bus Timing (80C196NU)

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Image 295

Intel 8XC196NP, Microcontroller manual Multiplexed System Bus Timing 80C196NU

Contents

8XC196NP, 80C196NU Microcontroller User’ Manual 8XC196NP, 80C196NU Microcontroller User’s Manual Intel Corporation Contents Chapter Programming Considerations Contents Chapter Ports EPA Functional Overview Programming the Serial Port8XC196NP, 80C196NU USER’S Manual Chapter Interfacing with External Memory Appendix C Registers Glossary Index Figures 10-7 Valid EPA Input Events 13-16 Tables 10-5 Example Control Register Settings and EPA Operations 8XC196NP and 80C196NU Signals Arranged by Function Guide to This Manual Page Chapter Guide to this Manual Manual Contents8XC196NP, 80C196NU USER’S Manual Addresses Notational Conventions and TerminologyItalics Related Documents Units of measureApplication Notes, Application Briefs, and Article Reprints Handbooks and Product InformationTitle Order Number MCS 96 Microcontroller Datasheets Automotive MCS 96 Microcontroller Datasheets Commercial/Express8XC196NP, 80C196NU USER’S Manual Intentionally Left Blank Intentionally Left Blank Technical Support World Wide WebProduct Literature Page Architectural Overview Page Typical Applications Chapter Architectural OverviewROM Device FeaturesBlock Diagram Features of the 8XC196NP and 80C196NURegister File CPU ControlCode Execution Register Arithmetic-logic Unit RaluInstruction Format Memory ControllerMultiply-accumulate 80C196NU Only Interrupt ServiceClock Circuitry 8XC196NP Internal TimingClock Circuitry 80C196NU 50 MHz State Times at Various Frequencies12.5 MHz 25 MHzMultiplier State Time PLLEN21Serial I/O SIO Port Event Processor Array EPA and Timer/CountersInternal Peripherals 1 I/O PortsPulse-width Modulator PWM Reducing Power ConsumptionSpecial Operating Modes Design Considerations for 80C196NP to 80C196NU Conversions Testing the Printed Circuit Board8XC196NP, 80C196NU USER’S Manual Advanced Math Features Page Enhanced Multiplication Instructions Chapter Advanced Math FeaturesInstructions Execution Time Saturation ModeOperating Modes Multiply/Accumulate Example CodeFractional Mode Accumulator Register ACC0x Accstat Accumulator Control and Status Register AccstatBit Function Number Mnemonic SME FME Effect of SME and FME Bit CombinationsDescription Programming Considerations Page Restrictions Overview of the Instruction SETOperand Type Definitions Operand Type No. Signed Possible Values AddressingByte Operands BIT OperandsSHORT-INTEGER Operands Integer Operands Word OperandsDOUBLE-WORD Operands Conditional Jumps LONG-INTEGER OperandsQUAD-WORD Operands Converting OperandsExtended Instructions Floating Point OperationsAddressing Modes ESTDefinition of Temporary Registers Direct AddressingImmediate Addressing Indirect AddressingIndirect Addressing with Autoincrement Extended Indirect AddressingExtended Indirect Addressing with Autoincrement Long-indexed Addressing Indexed AddressingIndirect Addressing with the Stack Pointer Short-indexed AddressingZero-indexed Addressing Extended Indexed AddressingExtended Zero-indexed Addressing Software Standards and Conventions Assembly Language Addressing Mode SelectionsExtended Addressing Design Considerations for 1-MBYTE DevicesAddressing 32-bit Operands Using RegistersAddressing 64-bit Operands Linking Subroutines Software Protection Features and Guidelines Memory Partitions Page Memory MAP Overview Chapter Memory PartitionsF0H FFH 2FH 1FH 0FH F1HFFH Memory Partitions80C196NP/NU External 83C196NP ROM Hex Description Addressing Modes XC196NP and 80C196NU Memory MapProgram Memory in Page FFH Program Memory Access for the 83C196NPExternal Memory Program and Special-purpose MemorySpecial-purpose Memory Special-purpose Memory Access for the 83C196NPXC196NP and 80C196NU Special-purpose Memory Addresses Interrupt and PTS Vectors Chip Configuration BytesPeripheral Special-function Registers SFRs Reserved Memory LocationsPeripheral SFRs 1F4EH 1F7EH1F7CH 1F7AHCPU SFRs Stack PointerAddress Description Addressing Modes Range Register File Memory AddressesGeneral-purpose Register RAM Stack Pointer SP80C196NU CPU SFRs Address High Odd Byte Low Even Byte CPU Special-function Registers SFRsCPU SFRs 8XC196NP CPU SFRs Address High Odd Byte Low Even Byte8XC196NP WindowingBit Function Selecting a WindowWSR HldenSelecting a Window of the Upper Register File Addressing a Location Through a Window Upper Register File 10. WindowsBase WSR or WSR1 Value WSR Value for Peripheral SFRs2.3 128-byte Windowing Example 11. Windowed Base Addresses2.1 32-byte Windowing Example 2.2 64-byte Windowing ExampleUnsupported Locations Windowing Example 8XC196NP Only Using the Linker Locator to Set Up a WindowType Base Length Alignment Windowing and Addressing Modes This listing shows the disassembled codeRemapping Internal ROM 83C196NP only Epcpc Accessing DataFetching Code and Data in the 1-MBYTE and 64-KBYTE Modes Fetching InstructionsFormation of Extended and Nonextended Addresses Code Fetches in the 64-Kbyte Mode Code Fetches in the 1-Mbyte Mode80C196NP and 80C196NU Data Fetches in the 1-Mbyte and 64-Kbyte ModesCE# Memory Configuration ExamplesExample 1 Using the 64-Kbyte Mode RD# WR#80C196NP and 80C196NU Unimplemented 12. Memory Map for the System in FigureAddress Description 80C196NP and 80C196NU External flash memory02FFFFH Example 2 a 64-Kbyte System with Additional Data StorageRD# WR# CE# Ffffffh D70 OE# WE#80C196NP and 80C196NU External RAM 13. Memory Map for the System in Figure01FFFFH Example 3 Using 1-Mbyte ModeOE# WE# OE# WRH# WRL# RD# 80C196NP and 80C196NU External memory 14. Memory Map for the System in FigureFbffffh Standard and PTS Interrupts Page Overview of Interrupts Chapter Standard and PTS InterruptsFlow Diagram for PTS and Standard Interrupts Interrupt Signals Interrupt Signals and RegistersInterrupt and PTS Control and Status Registers Ptssel Interrupt Sources and PrioritiesSpecial Interrupts IntpendSoftware Trap Interrupt Controller PTS ServiceInterrupt Sources, Vectors, and Priorities Unimplemented Opcode1.3 NMI External Interrupt PinsMultiplexed Interrupt Sources End-of-PTS InterruptsSituations that Increase Interrupt Latency Interrupt LatencyStandard Interrupt Latency Calculating LatencyStandard Interrupt Response Time PTS Interrupt Latency Programming the Interrupts PTS Mode Execution Time in State TimesExecution Times for PTS Cycles Ptssel Programming Considerations for Multiplexed InterruptsBit Mnemonic Interrupt PTS Vector EPA0 EXTINT1 EXTINT0 OVRTM2 OVRTM1 IntmaskBit Mnemonic Interrupt Standard Vector EPA3 EPA2 EPA1 Modifying Interrupt PrioritiesINTMASK1 NMI EXTINT3 EXTINT2RET Cseg AT 0FF200CH Determining the Source of an Interrupt Intpend Interrupt Pending Intpend RegisterINTPEND1 Initializing the PTS Control BlocksSingle Transfer PWM Toggle ModePWM Remap Mode Specifying the PTS CountPtssrv Selecting the PTS ModeEPA3 EPA2 EPA1 EXTINT0 OVRTM1 OVRTM2 Ptscon Single Transfer ModeAddress Ptspcb + Ptsdst Ptscb + PTS Single Transfer Mode Control BlockPtsdst HI Ptsdst LO Ptssrc HI Ptssrc LO Ptscon Ptscount Register Location Function8XC196NP, 80C196NU USER’S Manual Ptscount = 09H Block Transfer ModeSingle Transfer Mode Ptscb Block Transfer Mode PtscbPtsblock Ptscb + PTS Block Transfer Mode Control BlockIncrement the contents of Ptssrc after each byte or word PTSCONST2 PWM Toggle Mode PWM Remap ModePWM Modes Comparison of PWM Modes14. a Generic PWM Waveform PWM Toggle Mode ExamplePTSCONST1 HI = T1 HI PTSCONST1 LO = T1 LO PTSPTR1 HI = 1FH PWM Toggle Mode PtscbPTSCONST1 L PTSCONST2 HPTSCONST2 L PTSCONST1 HTmod Ptscon Ptscb +16. EPA and PTS Operations for the PWM Toggle Mode Example PWM Remap Mode Example PWM Remap Mode Ptscb PTSCONST1 HI PTSCONST1 LO PTSPTR1 HI PTSPTR1 LO Ptscon PTS PWM Remap Mode Control BlockPWM Tmod PTS PWM Remap Mode Control Block Register18. EPA and PTS Operations for the PWM Remap Mode Example Ports Page Port Bits Type I/O Ports OverviewBidirectional Ports Device I/O PortsPort Pin Special-function Associated Signals Bidirectional Port PinsBidirectional Port Control and Status Registers Bidirectional Port Operation8XC196NP, 80C196NU USER’S Manual Bidirectional Port Structure Sfdir Logic Table for Bidirectional Ports in I/O ModeBidirectional Port Pin Configurations Control Register Values for Each Configuration Bidirectional Port Pin Configuration ExamplePort Configuration Example HZ1 Bidirectional Port ConsiderationsP2.7/CLKOUT Eport Eport PinsPort Pin Extended-address Signal Type Design Considerations for External Interrupt Inputs10. Eport Control and Status Registers Eport OperationEport Block Diagram Open-drain Output Mode ResetOutput Enable Complementary Output ModeEport Structure Epmode Epdir Epreg Input Mode11. Logic Table for Eport in I/O Mode 12. Logic Table for Eport in Address Mode13. Configuration Register Settings for Eport Pins Configuring Eport PinsConfiguring Eport Pins for Extended-address Functions Configuring Eport Pins for I/OEport Status During Instruction Execution Eport ConsiderationsDesign Considerations Page Serial I/O SIO Port Page Serial I/O SIO Port Functional Overview SIO Block DiagramSerial Serial I/O Port Signals and RegistersSerial Port Signals Serial Port Control and Status RegistersSpbaud 1FBCH,1FBDH P1REG 1FD4HSbufrx 1FB8H Sbuftx 1FBAHSerial Port Modes Synchronous Mode ModeSpstatus 1FB9H Asynchronous Modes Modes 1, 2, Mode 0 TimingMode Serial Port Frames for ModeMode 2 and 3 Timings Serial Port Frames in Mode 2Programming the Baud Rate and Clock Source Configuring the Serial Port PinsProgramming the Serial Port Programming the Control RegisterPAR TB8 PRS REN PEN SpconPAR Bit Function SpconSpbaud Baud Rate Spbaud Register Value Note Error Mode Mode 1, 2 Spbaud Values When Using the Internal Clock at 25 MHz8A2BH 8A2CH Baud Rate Spbaud Register Value † Error ModeEnabling the Serial Port Interrupts Determining Serial Port StatusRPE/RB8 TXE SpstatusRPE/RB8 Serial I/O SIO Port Page Pulse-width Modulator Page PWM Functional Overview PWM Block Diagram 8XC196NP OnlyPWM Signals PWM Signals and RegistersPWM Control and Status Registers PWM Operation8XC196NP, 80C196NU USER’S Manual FFH EnabledProgramming the Frequency and Period E6HCLK1 CLK0 PWM Output Frequencies 8XC196NPPWM Output Frequencies 80C196NU CLK0CLK1 CLK0 Programming the Duty CycleCONREG0 FEHPWM Duty Cycle DisabledClock Prescaler PWM xCONTROL AddressPWM Output Alternate Functions PWM Output Alternate Port Function PWM Output Enabled WhenSample Calculations Enabling the PWM OutputsD/A Buffer Block Diagram Event Processor Array EPA Page EPA Functional Overview Chapter Event Processor Array EPAEPA EPA and TIMER/COUNTER Signals and RegistersEPA and Timer/Counter Signals Port Pin EPA SignalsEPA Control and Status Registers TIMER2 TIMER1EPA Timer/Counters TIMER/COUNTER Functional OverviewQuadrature Clocking Mode Cascade Mode Timer 2 OnlyQuadrature Mode Interface Quadrature Mode Truth Table EPA Channel Functional Overview Quadrature Mode Timing and CountA Single EPA Capture/Compare Channel Operating in Capture ModeEPA Simplified Input-capture Structure EPAxCON.0 Action Taken when a Valid Edge OccursAction taken when a valid edge occurs EPA OverrunsPreventing EPA Overruns Operating in Compare ModeGenerating a Low-speed PWM Output Generating a Medium-speed PWM Output Generating a High-speed PWM Output Generating the Highest-speed PWM Output Programming the EPA and TIMER/COUNTERSConfiguring the EPA and Timer/Counter Port Pins Programming the TimersT1CONTROL Prescaler Divisor Resolution †Clock Source Direction Source T2CONTROL Prescaler Resolution †Mode ROT ON/RT Example Control Register Settings and EPA OperationsProgramming the Capture/Compare Channels = 1 = 0 EPA xCON Address Reset State 00HROT ON/RT Compare Mode Action Capture Mode EventCompare Mode RT Capture Mode onROT Determining Event Status Enabling the EPA InterruptsEpamask Epapend † 12. EPA Interrupt Pending Epapend RegisterProgramming Examples for EPA Channels EPA Capture Event Program Unsigned char Unused Ptscon EPA PWM Output Program10-27 Page Minimum Hardware Considerations Page Signal Minimum Required SignalsMinimum Connections 11.1.2 I/O Port Pin Connections I/O Port Configuration GuidePort Where to Find Configuration Information Unused InputsMinimum Hardware Connections Noise Protection Tips Applying and Removing PowerOn-chip Oscillator Circuit ON-CHIP Oscillator CircuitryExternal Crystal Connections External Clock Connections Using AN External Clock SourceReset Timing Sequence Resetting the DeviceInternal Reset Circuitry Generating an External ResetMinimum Reset Circuit Issuing an Illegal Idlpd Key Operand Issuing the Reset RST InstructionPage Special Operating Modes Page Once Special Operating Mode Signals and RegistersOperating Mode Control Signals Port Pin Signal Type Description NameCCR0 Operating Mode Control and Status RegistersPort Pin Signal Type Description PLLEN21P2REG 1FD5H Reducing Power ConsumptionP2DIR 1FD3H P2MODE 1FD1HClock Control During Power-saving Modes 8XC196NP Clock Control During Power-saving Modes 80C196NU Idle ModeEnabling and Disabling Standby Mode Standby Mode 80C196NU onlyEntering Standby Mode Entering Powerdown Mode Exiting Standby ModePowerdown Mode Enabling and Disabling Powerdown ModeGenerating a Hardware Reset Exiting Powerdown ModeAsserting an External Interrupt Signal External RC Circuit Selecting C1 Typical Voltage on the RPD Pin While Exiting Powerdown Reserved Test Modes 80C196NU only Once ModePLLEN2 PLLEN1 C196NU Clock ModesPage Interfacing with External Memory Page Example of Internal and External Addresses Internal and External AddressesBit Demultiplexed Mode External Memory Interface SignalsExternal Memory Interface Signals Bit Multiplexed Bus ModeBHE# Bytes AccessedDescription Multiplexed With ALEReady Name Type Description Multiplexed WithEA# InstWRL# CHIP-SELECT UnitWRH# Register Address Description Mnemonic Chip-select RegistersDefining Chip-select Address Ranges Addrcom Address Reset StateRegister Address Register Address Reset Value Addrmsk Address Reset StateAddress Mbyte Kbyte Bytes Base Addresses for Several Sizes of the Address RangeFFB00H FFE00H FFD00H FFF00H Wait States Buscon Address Reset StateControlling Wait States, Bus Width, and Bus Multiplexing WS1 WS0Chip-select Unit Initial Conditions BUSCONx Addresses and Reset ValuesInitializing the Chip-select Registers Example of a Chip-select Setup Buscon Chip ContentsSram UartAddrcom Addrmsk Chip Configuration Registers and Chip Configuration BytesChip Address Size Number Contents Results for the Chip-select ExampleWS1 WS0 Demux BHE# CCR0WS0 WS1 Remap MODE64 CCR1Remap 13-17 BUS Width and Multiplexing Bit Multiplexed Bus Bit Demultiplexed BusALE ALE Bit Demultiplexed BusBit Multiplexed Bus 13.5.1 a 16-bit Example System CS# 13.5.2 16-bit Bus TimingsRD# Clkout ALE13.5.3 8-bit Bus Timings A190 Address AD158 High Address Wait States Ready Control Comparison of Multiplexed and Demultiplexed BusesBus Description Demultiplexed Bus ns† Multiplexed Bus ns† Symbol Definition 11. Ready Signal Timing DefinitionsBHE#, Inst Ready ALE14. Ready Timing Diagram Demultiplexed Mode 8XC196NP BUS-HOLD Protocol 15. Ready Timing Diagram Demultiplexed Mode 80C196NU12. HOLD#, HLDA# Timing Definitions Symbol ParameterDisabling the Bus-hold Protocol Enabling the Bus-hold ProtocolHold Latency Bus Cycle Type Regaining Bus ControlWRITE-CONTROL Modes 13. Maximum Hold LatencyBus Word/Byte Standard Write Strobe 14. Write Signals for Standard and Write Strobe ModesALE WR# WRL# BHE# WRH#18. Decoding WRL# and WRH# RD# WRH# WRL# System BUS AC Timing SpecificationsWE# OE# 20. Multiplexed System Bus Timing 8XC196NP 21. Multiplexed System Bus Timing 80C196NU 22. Demultiplexed System Bus Timing 8XC196NP 23. Demultiplexed System Bus Timing 80C196NU Deferred Bus-cycle Mode 80C196NU Only24. Deferred Bus-cycle Mode Timing Diagram 80C196NU Conditions Explanation of AC Symbols15. AC Timing Symbol Definitions Signals AC Timing DefinitionsSymbol Definition 8XC196Nx Meets These Specifications 13-44 13-45 Page Instruction Set Reference Page Appendix a Instruction SET Reference Opcode Table A-1. Opcode Map Left HalfTable A-1. Opcode Map Right Half Instruction Quotient Stored Flag Set if Quotient is Table A-2. Processor Status Word PSW FlagsMnemonic Description Value of Bits Shifted OffSymbol Description Table A-4. PSW Flag Setting SymbolsInstruction Jumps to Destination if Continues if Variable Description Table A-5. Operand VariablesC V VT ST PSW Flag SettingsTable A-6. Instruction Set Mnemonic OperationDest ← Dest and SRC Instruction FormatAndb PTRS, Cntreg BmovPC ← Dest Mnemonic Operation Instruction FormatCount ← Count DestClear WORD. Clears the value Compare BYTES. Subtracts the source Dest MOD SRC DIVDjnz Decrement and Jump if not Zero ← Dest MOD SRCDjnzw Decrement and Jump if not Zero Dpts Disable Peripheral TransactionEBR Ebmovi Extended Interruptable Block PTRS, CntregCount ← Cntreg Dstptr ← Ptrs + Dstptr ← Srcptr Ptrs ← Srcptr +Onto the stack, then adds to the program ELD Epts Enable Peripheral TransactionEXT SIGN-EXTEND Integer Into Long SRC, DestExtb Extb SIGN-EXTEND SHORT-INTEGER IntoIncrement WORD. Increments the value Word operand by JGE Jump if Signed Greater than or Mnemonic Operation Instruction FormatJLE Jump if Signed Less than or Equal JGTNegative flag is set, this instruction adds JNV Jump if Overflow Flag is Clear JNHJnvt Jnvt Jump if OVERFLOW-TRAP Flag isJVT JVT Jump if OVERFLOW-TRAP Flag is SETMbyte mode Kbyte modeMulb MULMulu MuluNegate INTEGER. Negates the value Dest ← Dest PSW Flag SettingsMulub NEGDest ← not Dest MnemonicORB Dest ← Dest or SRCPSW/INTMASK ← SP INTMASK1/WSR ← SPSP ← INTMASK1/WSR INTMASK1 ← SP ← PSW/INTMASK PSW/INTMASK ←Scall RSTWreg,#count SHR ShllRange of 0 to 31 1FH, inclusive. If Shral Shral Arithmetic Right Shift DoubleSkip Shrl Logical Right Shift DOUBLE-WORDSUB Rightmost operandSubcb Subtract Bytes with Borrow DEST, SRC SubbSubc Subtract Words with Borrow DEST, SRC SubcIndex and #MASK = Offset × Offset + Tbase = Dest PC ← Dest Tijmp TBASE, INDEX, #MASKSRC MnemonicDest ← Dest XOR SRC XORDecb Extb Incb Shrb Shlb Shrab Table A-7. Instruction OpcodesHex Code Instruction Mnemonic Clrb Notb NegbHex Code Instruction SET Reference 8XC196NP, 80C196NU USER’S Manual ST Direct ELD Indirect Arithmetic Group Direct Immediate Indirect Indexed Mnemonic Table A-8. Instruction Lengths and Hexadecimal OpcodesSubc Subcb Logical Direct Immediate Indirect Opcode Length Stack Direct Immediate Indirect Indexed MnemonicPOP Popa Popf Push Pusha Pushf Direct Immediate Data Direct ImmediateExtended Ebmovi ELD Eldb EST EstbLcall RET Jump Direct ImmediateEBR Ejmp Call Direct ImmediateJGE JGT JLE JLT JNC JNE JNH Jnst JNV Jnvt JST JVT Djnz Djnzw JBCPTS Shift Mnemonic Direct Immediate Indirect IndexedLength Opcode Special Mnemonic Direct Immediate IndirectMem Reg Table A-9. Instruction Execution Times in State TimesArithmetic Group Indirect Normal Autoinc Short Long Reg MemDIV Divb Divu Divub Mnemonic Direct Immed Normal Autoinc Short Long Reg MemLogical Normal Autoinc Short Stack Register IndirectReg Mem Autoinc Short Long Reg Mem Data Mnemonic Extended-indirect NormalExtended-indexed Indexed MnemonicLjmp Sjmp Tijmp Mnemonic Direct ImmedAutoinc Short Long Indirect Indexed Mnemonic Direct ImmedMnemonic Direct Conditional JumpMnemonic Short-Indexed ShiftImmed Indirect Indexed Special Mnemonic Direct Immed Indirect IndexedClrc Clrvt Idlpd NOP RST Setc SkipPage Signal Descriptions Page Table B-1 XC196NP and 80C196NU Signals Arranged by Function Functional Groupings of SignalsX8XC196NP Figure B-1 XC196NP 100-lead Sqfp PackageFigure B-2 XC196NP 100-lead QFP Package X8XC196NU Figure B-3 C196NU 100-lead Sqfp PackageFigure B-4 C196NU 100-lead QFP Package Column Heading Description Name Signal DescriptionsTable B-3. Signal Descriptions Table B-2. Description of Columns of Table B-3WRH# BREQ# Byte High Enable†EXTINT30 EPORT.30VSS HOLD#PLLEN1 PLLEN2 Name Type DescriptionVSS if either of the following conditions are true Asserted only during external memory writes RESET# Default ConditionsTable B-4. Definition of Status Symbols RESET# NP/NUBHE# WK1 Ready WK1 RESET# RPDWK1 EPORT.30 ALE WK0Registers Page Interrupts Chip ConfigurationTable C-1. Modules and Related Registers CPU EPATable C-2. Register Name, Address, and Reset Status 1FD6H Xxxx P1REG EPA3CONEPA2TIME EPA3TIMEWSR1 NU Xxxx SpbaudACC0x Table C-3. ACC0x Addresses and Reset ValuesACC0x Accstat AccstatSME FME Table C-4. Effect of SME and FME Bit CombinationsADDRCOMx Table C-5. ADDRCOMx Addresses and Reset ValuesAddrcom Address ADDRMSKx Address Table C-6 Reset State Table C-6. ADDRMSKx Addresses and Reset ValuesADDRMSKx BUSCONx Table C-7. BUSCONx Addresses and Reset ValuesBuscon Address CCR0 CCR0CCR1 CCR1CONREG0 CONREG0PIN3 PIN2 PIN1 PIN0 EpdirEpmode EpmodeXXH EppinX0H EpregEpamask EpamaskEpapend EpapendEPA xCON Address EPAxCONBit Function EPAxCON Address Table C-8Bit Function Number Register Address Reset Value Table C-8. EPAxCON Addresses and Reset ValuesEPAxTIME Table C-9. EPAxTIME Addresses and Reset ValuesIntmask IntmaskFF203EH EXTINT3 INTMASK1FF203CH EXTINT2 Intpend IntpendINTPEND1 INTPEND1150 One These bits are always equal to Ffffh OnesregOnesreg FfffhPIN7 PIN6 PIN5 PIN4 PIN3 PIN2 PIN1 PIN0 Table C-10. PxDIR Addresses and Reset ValuesPxDIR XDIR AddressTable C-12. Special-function Signals for Ports Table C-11. PxMODE Addresses and Reset ValuesPxMODE Bit Number Table C-13. PxPIN Addresses and Reset ValuesPxPIN XPIN AddressP1REG 1FD4H FFH P2REG 1FD5H P3REG 1FDCH P4REG 1FDDH Table C-14. PxREG Addresses and Reset ValuesPxREG PxREG Address Table C-14PSW PSWPSE Bit Function Number Mnemonic PSWPtssel PtsselFF200AH EXTINT1 PtssrvPWMxCONTROL Table C-15. PWMxCONTROL Addresses and Reset ValuesSbufrx SbufrxData Received Sbuftx SbuftxData to Transmit Xxxxh Spbaud SpbaudMode 1, 2 Baud Rate Spbaud Register Value Note Error ModeSpcon SpconSpstatus T1CONTROL T1CONTROLT2CONTROL T2CONTROLTable C-17. TIMERx Addresses and Reset Values TIMERxTimer Address Mnemonic Location WSRByte Windows Register Memory 00E0-00FFHRegister Memory 00E0-00FFH 00C0-00FFH PWM1CONTROL 1FB2H 7DH TIMER1 †TIMER2 † P4DIR 1FDBH 7EH 00FBH 3FH 00DBH 1FH P4MODE 1FD9HRegister Memory 0060-007FH 0040-007FH Mnemonic Location WSR10060-007FH 0040-007FH Mnemonic Location Spcon 1FBBH 7DH PWM0CONTROL 1FB0H 7DHSbuftx 1FBAH 7DH Spbaud 1FBCH 7DHZeroreg Zeroreg150 Zero This register is always equal to zero Page Glossary Page Glossary DOUBLE-WORD FET ISR PIC PLL PTS SFR Uart Index Page Index Index-2 Index-3 Index-4 Index-5 Index-6 Index-7 Index-8 Index-9 Index-10 Index-11 Index-12