Intel 8XC196NP Enabling the Bus-hold Protocol, Disabling the Bus-hold Protocol, Hold Latency

8XC196NP, 80C196NU USER’S MANUAL

If the 8XC196Nx has a pending external bus cycle while it is in hold (another device has control of the bus), it asserts BREQ# to request control of the bus. After the external device responds by releasing HOLD#, the 8XC196Nx exits hold and then deasserts BREQ# and HLDA#.

13.7.1 Enabling the Bus-hold Protocol

To use the bus-hold protocol, you must configure P2.3/BREQ#, P2.5/HOLD#, and P2.6/HLDA# to operate as special-function signals. BREQ# and HLDA# are active-low outputs; HOLD# is an active-low input.

You must also set the hold enable bit (HLDEN) in the window selection register (WSR.7) to en- able the bus-hold protocol. Once the bus-hold protocol has been selected, the port functions of P2.3, P2.5, and P2.6 cannot be selected without resetting the device. (During the time that the pins are configured to operate as special-function signals, their special-function values can be read from the P2_PIN.x bits.) However, the hold function can be dynamically enabled and disabled as described in “Disabling the Bus-hold Protocol.”

13.7.2 Disabling the Bus-hold Protocol

To disable hold requests, clear WSR.7. The 8XC196Nx does not take control of the bus immedi- ately after HLDEN is cleared. Instead, it waits for the current hold request to finish and then dis- ables the bus-hold feature and ignores any new requests until the bit is set again.

Sometimes it is important to prevent another device from taking control of the bus while a block of code is executing. One way to protect a code segment is to clear WSR.7 and then execute a JBC instruction to check the status of the HLDA# signal. The JBC instruction prevents the RALU from executing the protected block until current hold requests are serviced and the hold feature is disabled. This is illustrated in the following code:

	DI		;Disable interrupts to prevent
			;code interruption
	PUSH	WSR	;Disable hold requests and
	LDB	WSR,#1FH	;window Port 2
WAIT:	JBC	P2_PIN,6, WAIT	;Check the HLDA# signal. If set,
			;add protected instruction here
	POP	WSR	;Enable hold requests
	EI		;Enable interrupts

13.7.3 Hold Latency

When an external device asserts HOLD#, the 8XC196Nx finishes the current bus cycle and then asserts HLDA#. The time it takes the device to assert HLDA# after the external device asserts HOLD# is called hold latency (see Figure 13-16 on page 13-31). Table 13-13 lists the maximum hold latency for each type of bus cycle.

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