Intel Microcontroller, 8XC196NP manual Clock Circuitry 80C196NU

8XC196NP, 80C196NU USER’S MANUAL
		Disable
		PLL
		(Powerdown)
XTAL1	FXTAL1					Phase	Filter
						Comparator
	XTAL1
	F	XTAL1				Phase-
XTAL2						locked
						Oscillator
		2F
	Disable	XTAL1	Disable Clock Input			Phase-locked Loop
	Oscillator		(Powerdown)
						Clock Multiplier
		4F
	(Powerdown)
			f Divide-by-two
			Circuit
	PLLEN1		f		Disable Clocks
			2	(Standby, Powerdown)
	PLLEN2					Peripheral Clocks (PH1, PH2)
			Clock			CLKOUT
			Generators
						CPU Clocks (PH1, PH2)
					Disable Clocks
				(Idle, Standby, Powerdown)
							A3063-02
	Figure 2-4.		Clock Circuitry (80C196NU)

For both the 8XC196NP and 80C196NU, the rising edges of PH1 and PH2 generate CLKOUT (Figure 2-5). The clock circuitry routes separate internal clock signals to the CPU and the periph- erals to provide flexibility in power management. (“Reducing Power Consumption” on page 12-3 describes the power management modes.) It also outputs the CLKOUT signal on the CLKOUT pin. Because of the complex logic in the clock circuitry, the signal on the CLKOUT pin is a de- layed version of the internal CLKOUT signal. This delay varies with temperature and voltage.

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