Intel 80C196NU, 8XC196NP, Microcontroller Symbol Definition 8XC196Nx Meets These Specifications

	INTERFACING WITH EXTERNAL MEMORY
	Table 13-16. AC Timing Definitions (Continued)
Symbol	Definition
	The 8XC196Nx Meets These Specifications
f	Operating frequency
	Frequency of the signal input on the XTAL1 pin times the clock multiplier (x). For the
	8XC196NP, x is always 1; for the 80C196NU, x is 1, 2, or 4, depending on the clock mode. The
	internal bus speed of the device is ½ f.
t	Operating period (1/f)
	All AC Timings are referenced to t.
TAVLL	Address Setup to ALE Low
	Length of time ADDRESS is valid before ALE falls. Use this specification when designing the
	external latch.
TAVRL	Address Setup to RD# Low
	Length of time ADDRESS is valid before RD# falls.
TAVWL	Address Setup to WR# Low
	Length of time ADDRESS is valid before WR# falls.
TCHCL	CLKOUT High Period
	Needed in systems that use CLKOUT as clock for external devices.
TCHWL	CLKOUT High to WR# Low
	Time between CLKOUT going high and WR# going active.
TCLCL	CLKOUT Cycle Time
	Normally 2t.
TCLLH	CLKOUT Falling to ALE Rising
	Use to derive other timings.
TLHLH	ALE Cycle Time
	Minimum time between ALE pulses.
TLHLL	ALE High Period
	Use this specification when designing the external latch.
TLLAX	Address Hold after ALE Low
	Length of time ADDRESS is valid after ALE falls. Use this specification when designing the
	external latch.
TLLCH	ALE Falling to CLKOUT Rising
	Use to derive other timings.
TLLRL	ALE Low to RD# Low
	Length of time after ALE falls before RD# is asserted. Could be needed to ensure proper
	memory decoding takes place before a device is enabled.
TLLWL	ALE Low to WR# Low
	Length of time after ALE falls before WR# is asserted. Could be needed to ensure proper
	memory decoding takes place before a device is enabled.

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