Intel Microcontroller, 80C196NU, 8XC196NP manual Chapter Guide to this Manual, Manual Contents

CHAPTER 1

GUIDE TO THIS MANUAL

This manual describes the 8XC196NP and 80C196NU embedded microcontrollers. It is intended for use by both software and hardware designers familiar with the principles of microcontrollers. This chapter describes what you’ll find in this manual, lists other documents that may be useful, and explains how to access the support services we provide to help you complete your design.

1.1MANUAL CONTENTS

This manual contains several chapters and appendixes, a glossary, and an index. This chapter, Chapter 1, provides an overview of the manual. This section summarizes the contents of the re- maining chapters and appendixes. The remainder of this chapter describes notational conventions and terminology used throughout the manual, provides references to related documentation, de- scribes customer support services, and explains how to access information and assistance.

Chapter 2 — Architectural Overview — provides an overview of the device hardware. It de- scribes the core, internal timing, internal peripherals, and special operating modes.

Chapter 3 — Advanced Math Features — describes the advanced mathematical features of the 80C196NU. The 80C196NU is the first member of the MCS® 96 microcontroller family to in- corporate enhanced 16-bit multiplication instructions for performing multiply-accumulate oper- ations and a dedicated, 32-bit accumulator register for storing the results of these operations. The accumulator and the enhanced instructions combine to decrease the amount of time required to perform multiply-accumulate operations. The instructions and accumulator support signed and unsigned integers as well as signed fractional data.

Chapter 4 — Programming Considerations — provides an overview of the instruction set, de- scribes general standards and conventions, and defines the operand types and addressing modes supported by the MCS® 96 microcontroller family. (For additional information about the instruc- tion set, see Appendix A.)

Chapter 5 — Memory Partitions — describes the addressable memory space of the device. It describes the memory partitions, explains how to use windows to increase the amount of memory that can be accessed with direct addressing, and provides examples of memory configurations.

Chapter 6 — Standard and PTS Interrupts — describes the interrupt control circuitry, priority scheme, and timing for standard and peripheral transaction server (PTS) interrupts. It also ex- plains interrupt programming and control.

Chapter 7 — I/O Ports — describes the input/output ports and explains how to configure the ports for input, output, or special functions.

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