Intel 80C196NU, 8XC196NP manual Enabling the EPA Interrupts, Determining Event Status, Epamask

8XC196NP, 80C196NU USER’S MANUAL

10.6 ENABLING THE EPA INTERRUPTS

The EPA generates four individual event interrupts, EPA3:0, from the four capture/compare chan- nels and two timer interrupts, OVRTM1 and OVRTM2, from timer 1 and timer 2. These inter- rupts are directly mapped into the two 8-bit interrupt pending registers (INT_PEND and INT_PEND1). The four separate capture overrun interrupts from EPA3:0 are multiplexed and mapped into two bits in INT_PEND1. The capture overrun interrupts from EPA0 and EPA1 are multiplexed and mapped into OVR0_1 (bit 4) of INT_PEND1; the capture overrun interrupts from EPA2 and EPA3 are multiplexed and mapped into OVR2_3 (bit 5) of INT_PEND1. To en- able the interrupts, set the corresponding bits in the the two 8-bit interrupt mask registers (INT_MASK and INT_MASK1). To enable the individual sources of the capture overrun inter- rupts OVR0_1 and OVR2_3, set the corresponding bits in the EPA mask register (EPA_MASK). (Chapter 6, “Standard and PTS Interrupts,” discusses the interrupts in greater detail.)

EPA_MASK	Address:	1F9CH
	Reset State:	AAH

The EPA interrupt mask (EPA_MASK) register enables or disables (masks) the multiplexed EPA3:0 overrun interrupts (OVR3:0).

7

— OVR3 — OVR2

0

— OVR1 — OVR0

Bit	Bit	Function
Number	Mnemonic
7, 5, 3, 1	—	Reserved; for compatibility with future devices, write zeros to these bits.
6, 4, 2, 0	OVR3	Setting this bit enables the corresponding source as a shared overrun
	OVR2	interrupt source. The shared overrun interrupts (OVR0_1 and OVR2_3)
	OVR1	are enabled by setting their interrupt enable bits in the interrupt mask 1
	OVR0	(INT_MASK1) register.

Figure 10-11. EPA Interrupt Mask (EPA_MASK) Register

10.7 DETERMINING EVENT STATUS

In compare mode, an interrupt pending bit is set each time a match occurs on an enabled event (even if the interrupt is specifically masked in the mask register). In capture mode, an interrupt pending bit is set each time a programmed event is captured and the event time moves from the capture buffer to the EPAx_TIME register. If the capture buffer is full when an event occurs, an overrun interrupt pending bit is set.

Timer overflows and capture overruns also set interrupt pending bits. You can mask the interrupts by clearing bits in EPA_MASK (Figure 10-11), INT_MASK, and INT_MASK1. If an interrupt is masked, software can still poll the interrupt pending registers to determine whether an event has occurred.

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