Intel 8XC196NP, 80C196NU, Microcontroller manual Pic Pll

nonvolatile memory

npn transistor

p-channel FET

p-type material

PC phase-locked loop

PIC

PLL

prioritized interrupt

program memory

protected instruction

GLOSSARY

Read-only memory that retains its contents when power is removed. Many MCS® 96 microcontrollers are available with either masked ROM, EPROM, or OTPROM. Consult the Automotive Products or Embedded Microcontrollers databook to determine which type of memory is available for a specific device.

A transistor consisting of one part p-type material and two parts n-type material.

Afield-effect transistor with a p-type conducting path.

Semiconductor material with introduced impurities (doping) causing it to have an excess of positively charged carriers.

Program counter.

A component of the clock generation circuitry. The phase-locked loop (PLL) and the two input pins (PLLEN1 and PLLEN2) combine to enable the device to attain its maximum operating frequency with an external clock whose frequency is either equal to, one-half, or one-fourth that maximum frequency or with an external oscillator whose frequency is either one-half or one-fourth that maximum frequency.

Programmable interrupt controller. The module responsible for handling interrupts that are to be serviced by interrupt service routines that you provide. Also called simply the interrupt controller.

See phase-locked loop.

Any maskable interrupt or nonmaskable NMI. Two of the nonmaskable interrupts (unimplemented opcode and software trap) are not prioritized; they vector directly to the interrupt service routine when executed.

A partition of memory where instructions can be stored for fetching and execution.

An instruction that prevents an interrupt from being acknowledged until after the next instruction executes. The protected instructions are DI, EI, DPTS, EPTS, POPA, POPF, PUSHA, and PUSHF.

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