Intel 8XC196NP Bidirectional Port Operation, Bidirectional Port Control and Status Registers

I/O PORTS

Table 7-3. Bidirectional Port Control and Status Registers

Mnemonic	Address		Description
P1_DIR	1FD2H	Port x Direction
P2_DIR	1FCBH	Each bit of Px_DIR controls the direction of the corresponding pin.
P3_DIR	1FDAH
		0 = complementary output (output only)
P4_DIR	1FDBH
		1 =	input or open-drain output (input, output, or bidirectional)
			Open-drain outputs require external pull-ups.
P1_MODE	1FD0H	Port x Mode
P2_MODE	1FC9H	Each bit of Px_MODE controls whether the corresponding pin
P3_MODE	1FD8H
		functions as a standard I/O port pin or as a special-function signal.
P4_MODE	1FD9H
		0 =	standard I/O port pin
		1 =	special-function signal
P1_PIN	1FD6H	Port x Input
P2_PIN	1FCFH	Each bit of Px_PIN reflects the current state of the corresponding
P3_PIN	1FDEH
		pin, regardless of the pin configuration.
P4_PIN	1FDFH
P1_REG	1FD4H	Port x Data Output
P2_REG	1FCDH	For an input, set the corresponding Px_REG bit.
P3_REG	1FDCH
		For an output, write the data to be driven out by each pin to the
P4_REG	1FDDH
		corresponding bit of Px_REG. When a pin is configured as standard
		I/O (Px_MODE.y = 0), the result of a CPU write to Px_REG is
		immediately visible on the pin. When a pin is configured as a
		special-function signal (Px_MODE.y = 1), the associated on-chip
		peripheral or off-chip component controls the pin. The CPU can still
		write to Px_REG, but the pin is unaffected until it is switched back to
		its standard I/O function.
		This feature allows software to configure a pin as standard I/O (clear
		Px_MODE.y), initialize or overwrite the pin value, then configure the
		pin as a special-function signal (set Px_MODE.y). In this way, initial-
		ization, fault recovery, exception handling, etc., can be done without
		changing the operation of the associated peripheral.

7.2.1Bidirectional Port Operation

Figure 7-1 shows the logic for driving the output transistors, Q1 and Q2. On ports 1, 2, and 3, Q1 can source at least –3 mA at V CC – 0.7 volts. On port 4, which has a high-current sink capability for the PWMs, Q1 can source at least –3 mA at 0.45 volts. Q2 can sink at least 10 mA at 0.45 volts. (Consult the datasheet for specifications.)

In I/O mode (selected by clearing Px_MODE.y), Px_REG and Px_DIR are input to the multiplex- ers. These signals combine to drive the gates of Q1 and Q2 so that the output is high, low, or high impedance. Table 7-4 is a logic table for I/O operation of these ports.

7-3