Intel 8XC196NP, 80C196NU, Microcontroller manual Instruction Format, Dest ← Dest and SRC, Andb

8XC196NP, 80C196NU USER’S MANUAL

Table A-6. Instruction Set (Continued)

Mnemonic				Operation					Instruction Format
ADDCB	ADD BYTES WITH CARRY. Adds the source								DEST, SRC
	and destination byte operands and the carry							ADDCB	breg, baop
	flag (0 or 1) and stores the sum into the
								(101101aa) (baop) (breg)
	destination operand.
	(DEST) ← (DEST) + (SRC) + C
			PSW Flag Settings
		Z	N	C	V	VT	ST
		↓	✓	✓	✓	−	—
AND	LOGICAL AND WORDS. ANDs the source								DEST, SRC
(2 operands)	and destination word operands and stores							AND	wreg, waop
	the result into the destination operand. The
								(011000aa) (waop) (wreg)
	result has ones in only the bit positions in
	which both operands had a “1” and zeros in
	all other bit positions.
	(DEST) ← (DEST) AND (SRC)
			PSW Flag Settings
		Z	N	C	V	VT	ST
		✓	✓	0	0	—	—
AND	LOGICAL AND WORDS. ANDs the two								DEST, SRC1, SRC2
(3 operands)	source word operands and stores the result							AND	Dwreg, Swreg, waop
	into the destination operand. The result has
								(010000aa) (waop) (Swreg) (Dwreg)
	ones in only the bit positions in which both
	operands had a “1” and zeros in all other bit
	positions.
	(DEST) ← (SRC1) AND (SRC2)
			PSW Flag Settings
		Z	N	C	V	VT	ST
		✓	✓	0	0	—	—
ANDB	LOGICAL AND BYTES. ANDs the source								DEST, SRC
(2 operands)	and destination byte operands and stores the							ANDB	breg, baop
	result into the destination operand. The result
								(011100aa) (baop) (breg)
	has ones in only the bit positions in which
	both operands had a “1” and zeros in all other
	bit positions.
	(DEST) ← (DEST) AND (SRC)
			PSW Flag Settings
		Z	N	C	V	VT	ST
		✓	✓	0	0	—	—

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